We will decide with subtarget support whether we ever use an i64 register
class.

llvm-svn: 23734

llvm-svn: 23733

llvm-svn: 23731

llvm-svn: 23727

llvm-svn: 23726

llvm-svn: 23681

can be used by other targets.  For those targets that want to use it,
have at.  :)

llvm-svn: 23680

This seems useful from the original patch that added the function.  If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

llvm-svn: 23676

the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.

llvm-svn: 23670

merge, and using subtarget info for ptr size.

llvm-svn: 23668

llvm-svn: 23666

is faster and uses less stack space.  This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel

llvm-svn: 23664

classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

llvm-svn: 23654

llvm-svn: 23652

llvm-svn: 23650

llvm-svn: 23649

llvm-svn: 23648

helps but not enough.

Start pulling cases out of PPC32DAGToDAGISel::Select.  With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes).  Pulling this first function out gets us down to 8224.  More
to come :(

llvm-svn: 23647

llvm-svn: 23644

llvm-svn: 23643

llvm-svn: 23637

llvm-svn: 23621

for globals

llvm-svn: 23608

llvm-svn: 23594

llvm-svn: 23593

llvm-svn: 23592

compile with an assertion that the tables are not sorted!

llvm-svn: 23591

the comparison to be 64-bits.  This is fine because extensions from float
to double are free.

llvm-svn: 23589

split the FSEL family into 4 things instead of just two.

llvm-svn: 23588

llvm-svn: 23587

llvm-svn: 23585

we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.

llvm-svn: 23582

llvm-svn: 23581

llvm-svn: 23578

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577

llvm-svn: 23572

llvm-svn: 23571

llvm-svn: 23569

llvm-svn: 23564

trim down the target info structs now that we have a preferred spill register class for each callee save register

Why is V9 maintaining these tables manually? ugh!

llvm-svn: 23561