llvm-svn: 115408

Now that PassInfo and Pass::ID have been separated, move the rest of the passes over to the new registration API.

llvm-svn: 111815

llvm-svn: 111540

llvm-svn: 110460

llvm-svn: 110454

When a physical register is in use, some alias of that register has a live
interval with a relevant live range. That is the sad state of intervals after
physreg coalescing of subregs, and it is good enough for correct register
allocation.

llvm-svn: 110452

llvm-svn: 110410

LiveVariables becomes horribly wrong while the coalescer is running, but the
analysis is not zapped until after the coalescer pass has run. This causes tons
of false reports when calling verify form the coalescer.

llvm-svn: 110402

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.

Stuff we don't check yet:

- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?

llvm-svn: 110386

be killed before being redefined.

These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.

llvm-svn: 110362

- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.

llvm-svn: 106344

The old approach was wrong. It had an off-by-one error.

llvm-svn: 104034

- Kill is implicit when use and def registers are identical.
- Only virtual registers can differ.

Add a -verify-fast-regalloc to run the verifier before the fast allocator.

llvm-svn: 103797

llvm-svn: 101376

MachineBasicBlock::livein_iterator a const_iterator, because
clients shouldn't ever be using the iterator interface to
mutate the livein set.

llvm-svn: 101147

llvm-svn: 100709

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

A phi operand that is implicitly defined in a predecessor becomes an undefined
register after phi elimination. This causes a lot of false positives when the
verifier is checking if live-in registers are live-out from all predecessors.

Removing the verifier checks seems like a better solution than insisting on
IMPLICIT_DEF instructions in predecessor blocks.

llvm-svn: 92769

These checks would often trigger on unreachable statements inserted by
bugpoint, leading it astray.

It would be nice if we could distinguish unreachable blocks from errors.

llvm-svn: 91923

ARM uses these to indicate predicates.

llvm-svn: 91922

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428

Verify LiveVariables information when present.

llvm-svn: 89241

llvm-svn: 88706

llvm-svn: 88704

 - Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

llvm-svn: 83474

llvm-svn: 83285

The machine code verifier did not check for explicit operands correctly. It
used MachineInstr::getNumExplicitOperands, but that method may cheat and use
the declared count in the TargetInstrDesc.

Now we check the explicit operands one at a time in visitMachineOperand.

llvm-svn: 82652

The machine code verifier no longer tolerates phi instructions with noop
operands. All MBBs on a phi instruction must be in the CFG.

llvm-svn: 82448

tolerant of blocks that end with "unreachable".

llvm-svn: 80270

do extra checking when it succeeds, as those are cases where
CodeGen will be doing particularly interesting CFG modifications.

llvm-svn: 80196

MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813

upgrading a few things to use raw_ostream

llvm-svn: 79811

instead of as two bools.  Use this to add a F_Append flag
which has the obvious behavior.

Other unrelated changes conflated into this patch:

1. REmove EH stuff from llvm-dis and llvm-as, the try blocks
   are dead.
2. Simplify the filename inference code in llvm-as/llvm-dis,
   because raw_fd_ostream does the right thing with '-'.
3. Switch machine verifier to use raw_ostream instead of ostream
   (Which is the thing that needed append in the first place).

llvm-svn: 79807

llvm-svn: 79801

So far these registers are simply tracked as if they were live-in.

llvm-svn: 78912