them are generic changes.

- Use the "fast" flag that's already being passed into the asm printers instead
  of shoving it into the DwarfWriter.

- Instead of calling "MI->getParent()->getParent()" for every MI, set the
  machine function when calling "runOnMachineFunction" in the asm printers.

llvm-svn: 65379

llvm-svn: 63988

being both a namespace and a variable name.

llvm-svn: 60208

special-purpose hook to a new pass. Also, add check to see if any
x87 virtual registers are used, to avoid doing any work in the
common case that no x87 code is needed.

llvm-svn: 59190

target-independent code to target-specific code. This prevents it
from running on targets that aren't using fast-isel.

In addition to saving compile time, this addresses the problem
that not all targets are prepared for it. In order to use this
pass, all instructions must declare all their fixed uses and
defs of physical registers.

llvm-svn: 58144

and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

require RIP-relative addressing and use it to fix a bug
in X86FastISel in x86-64 PIC mode, where it was trying to
use base/index registers with RIP-relative addresses. This
fixes a bunch of x86-64 testsuite failures.

llvm-svn: 56676

llvm-svn: 56621

llvm-svn: 56607

llvm-svn: 56585

llvm-svn: 55092

Move X86 assembler printers into separate directory. This allows JIT-only users not to link it in (use 'x86codegen' llvm-config arg for this)

llvm-svn: 54886

llvm-svn: 54700

model, except for external calls; this makes
addressing modes PC-relative.  Incomplete.

The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.

llvm-svn: 54656

llvm-svn: 53299

llvm-svn: 52613

X86CodeEmitter should not set PIC style to None at initialization time. This will break codegen if relocation model is changed to PIC_ later.

llvm-svn: 51455

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

Be over-conservative: scan for all used virtual registers and calculate maximal stack alignment in assumption, that there will be spill of vector register.

llvm-svn: 50167

llvm-svn: 50166

llvm-svn: 48704

llvm-svn: 48703

that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256

llvm-svn: 47736

llvm-svn: 47703

llvm-svn: 47369

llvm-svn: 45734

llvm-svn: 45418

llvm-svn: 45313

llvm-svn: 45312

llvm-svn: 45304

llvm-svn: 40878

Darwin (which makes size within a struct==96)

llvm-svn: 40796

(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792

llvm-svn: 40123

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 34520

Patch by Scott Michel.

llvm-svn: 34266

definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).

llvm-svn: 34034