the name prefix when we change them from internal to external.  This allows bugpointing
of codegen miscompilations to work more reliably on Darwin.

llvm-svn: 53236

soft float.

llvm-svn: 53231

llvm-svn: 53230

parameter attributes.

llvm-svn: 53228

llvm-svn: 53227

llvm-svn: 53226

argument number.

llvm-svn: 53225

Call and Invoke in a single method instead of having it hardcoded in multiple
places.

llvm-svn: 53224

call attributes.

llvm-svn: 53223

1) evaluate [v]fcmp true/false with undefs to true or false instead
   of undef.
2) fix vector comparisons with undef to return a vector result instead 
   of i1
3) fix vector comparisons with evaluatable results to return vector
   true/false instead of i1 true/false (PR2529)

llvm-svn: 53220

llvm-svn: 53218

llvm-svn: 53217

llvm-svn: 53215

llvm-svn: 53213

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

and reused across SelectionDAGs.

This drastically reduces the number of calls to malloc/free made during
instruction selection, and improves memory locality.

llvm-svn: 53211

for handling bookkeeping for deleted objects, as well as the alist class
template, for keeping lists of objects allocated from Recyclers, and some
related utilities.

llvm-svn: 53210

llvm-svn: 53209

ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.

llvm-svn: 53208

TargetRegisterDesc::Name field is the same as the abstract register name. There is no need for targets to specify register names in addition to their AsmName's.

llvm-svn: 53207

llvm-svn: 53206

getTargetNode and SelectNodeTo to reduce duplication, and to
make some of the getTargetNode code available to SelectNodeTo.
Use SelectNodeTo instead of getTargetNode in several new
interesting cases, as it mutates nodes in place instead of
creating new ones.

This triggers some scheduling behavior differences due to nodes
being presented to the scheduler in a different order. Some of the
arbitrary scheduling decisions it makes are now arbitrarily made
differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll,
where a trivial scheduling difference led to a trivial register
allocation difference.

llvm-svn: 53203

llvm-svn: 53202

properly track dead nodes that are on the original SDNode's operand
list but not the new one, and have no other uses.

llvm-svn: 53201

#include dependency on Support/MathExtras.h in the header file.

llvm-svn: 53200

pool-allocating MachineInstrs.

llvm-svn: 53198

llvm-svn: 53197

llvm-svn: 53196

and rearranging the fields.

llvm-svn: 53195

their cleanup code. 

llvm-svn: 53194

1. LSR runOnLoop is always returning false regardless if any transformation is made.
2. AddUsersIfInteresting can create new instructions that are added to DeadInsts. But there is a later early exit which prevents them from being freed.

llvm-svn: 53193

llvm-svn: 53192

llvm-svn: 53190

llvm-svn: 53189

llvm-svn: 53188

llvm-svn: 53187

simple const SDOperand*, which is what's usually needed.

For AddNodeIDOperands, which is small, just duplicate the function to
accept an SDUse*.

For SelectionDAG::getNode - Add an overload that accepts SDUse* that
copies the operands into a temporary SDOperand array, but also has
special-case checks for 0 through 3 operands to avoid the copy in
the common cases.

llvm-svn: 53183

all happened be unnecessary.

llvm-svn: 53182

llvm-svn: 53181

llvm-svn: 53180