The backend already knew this trick.

llvm-svn: 132915

we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880

memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869

rdar://9431466

llvm-svn: 132864

CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856

PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.

llvm-svn: 132826

Chris fixed this README a while back by changing how clang generates code for structs like the given struct.

llvm-svn: 132815

causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811

VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802

llvm-svn: 132795

Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.

llvm-svn: 132789

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781

llvm-svn: 132777

Patch by Pekka Jaaskelainen. 

llvm-svn: 132774

llvm-svn: 132768

No functional change.

Part of PR6965

llvm-svn: 132763

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132756

llvm-svn: 132726

llvm-svn: 132725

- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724

llvm-svn: 132718

llvm-svn: 132717

Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:

- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703

rdar://problem/9556069

llvm-svn: 132699

load.  rdar://problem/6373334

llvm-svn: 132696

rdar://problem/5993888

llvm-svn: 132606

Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601

addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561

- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552

Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.

rdar://9431157

llvm-svn: 132522

Part of rdar://9119939

llvm-svn: 132510

allocation orders.

llvm-svn: 132509

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

llvm-svn: 132486

llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

No functional change.

llvm-svn: 132455

llvm-svn: 132451