The backend already knew this trick.

llvm-svn: 132915

llvm-svn: 132914

llvm-svn: 132913

llvm-svn: 132912

llvm-svn: 132911

llvm-svn: 132910

llvm-svn: 132909

llvm-svn: 132908

intrinsics. In fact, we'll optimize a bitcast to that when possible. Detect it
when looking for the lifetime intrinsics.

No test case, noticed by inspection.

llvm-svn: 132906

In particular, don't spill dirty registers only to satisfy a hint. It is
not worth it.

The attached test case provides an example where the fast allocator
would spill a register when other registers are available.

llvm-svn: 132900

llvm-svn: 132899

having.

llvm-svn: 132898

InstCombine: Shrink ((zext X) & C1) == C2 to fold away the cast if the "zext" and the "and" have one use.

llvm-svn: 132897

llvm-svn: 132896

Only 163 days late!

llvm-svn: 132895

types such as i33 were rounded to i32. Originated from Duncan's testcase.

llvm-svn: 132893

Instead of scalarizing, and doing an element-by-element truncat, use vector
truncate.
Add support for scalarization of vectors:  i8 -> <1 x i1> (from Duncan's
testcase).

llvm-svn: 132892

element type is found.
This fix addresses some of the tests in Duncan's testcase (forthcoming).

llvm-svn: 132891

Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

llvm-svn: 132888

These computations have been moved to CodeGenRegisters.cpp.

llvm-svn: 132887

The constant hash tables for sub-registers and overlaps are generated
the same way, so extract a function to generate and print the hash
table.

Also use the information computed by CodeGenRegisters.cpp instead of the
locally data.

llvm-svn: 132886

Add a triple to the tests.

llvm-svn: 132885

llvm-svn: 132884

llvm-svn: 132883

we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
  defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
  before any of its sub-registers. When the sub-register graph is not a
  tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
  number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

llvm-svn: 132881

functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880

llvm-svn: 132876

llvm-svn: 132872

llvm-svn: 132871

memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869

Patch by: Jakub Staszak!

Introduces BranchProbability. Changes unsigned to uint32_t all over and
uint64_t only when overflow is expected.

llvm-svn: 132867

Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

llvm-svn: 132865

rdar://9431466

llvm-svn: 132864

llvm-svn: 132863

default, since it usually has very few elements. This speeds up
alias queries in many cases, because AliasCache.clear() doesn't
have to visit as many buckets.

llvm-svn: 132862

<rdar://problem/9583891>

llvm-svn: 132860

llvm-svn: 132857

CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856

comment on their meaning.

llvm-svn: 132854