llvm-svn: 81909

Another try at early partial coalescing. Identity phi source copies (their sources are defined by phi join def) are coalesced. And the phi join copy is backward copy propagated into the other copies.

Still miscompiling some tests. :-(

llvm-svn: 81849

Add early coalescing to liveintervals. This is work in progress and is known to miscompute some tests. Read it at your own rish, I have aged 10 year while writing this.

The gist of this is if source of some of the copies that feed into a phi join is defined by the phi join, we'd like to eliminate them. However, if any of the non-identity source overlaps the live interval of the phi join then the coalescer won't be able to coalesce them. The early coalescer's job is to eliminate the identity copies by partially-coalescing the two live intervals.

llvm-svn: 81796

llvm-svn: 81605

llvm-svn: 81598

a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040

update all code that this affects.

llvm-svn: 79830

MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813

llvm-svn: 79795

llvm-svn: 79752

Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg.

llvm-svn: 78620

llvm-svn: 78151

Re-apply LiveInterval index dumping patch, with fixes suggested by Bill
and others.

llvm-svn: 78003

llvm-svn: 77754

 - Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019

llvm-svn: 76963

Constify the key in Mi2IndexMap.

llvm-svn: 76801

llvm-svn: 76646

Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands.

llvm-svn: 76223

llvm-svn: 76100

Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640

Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379

and abort()/exit() -> llvm_report_error().

llvm-svn: 75363

llvm-svn: 75267

as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.

llvm-svn: 75097

Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.

Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601

Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.

llvm-svn: 74580

Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518

by Evan.

llvm-svn: 74370

llvm-svn: 73750

llvm-svn: 73727

llvm-svn: 73634

Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

llvm-svn: 72729

entries as there are basic blocks in the function.  LiveVariables::getVarInfo
creates a VarInfo struct for every register in the function, leading to
quadratic space use.  This patch changes the BitVector to a SparseBitVector,
which doesn't help the worst-case memory use but does reduce the actual use in
very long functions with short-lived variables.

llvm-svn: 72426

In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However,  reloads and restores might be folded into uses / defs and freed registers might not be used at all.

VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.

llvm-svn: 70787

llvm-svn: 70245

Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.

llvm-svn: 70213