llvm-svn: 140784

llvm-svn: 140783

This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

llvm-svn: 140776

llvm-svn: 140774

llvm-svn: 140773

This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

llvm-svn: 140772

llvm-svn: 140769

llvm-svn: 140767

Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

llvm-svn: 140762

llvm-svn: 140761

llvm-svn: 140758

llvm-svn: 140755

llvm-svn: 140754

llvm-svn: 140753

This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.

llvm-svn: 140751

llvm-svn: 140745

The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

llvm-svn: 140744

"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741

It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735

ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733

multiclasses.

llvm-svn: 140731

Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.

llvm-svn: 140730

llvm-svn: 140726

llvm-svn: 140723

llvm-svn: 140722

llvm-svn: 140721

NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works.  Use (void*)0 instead.  PR11002.

llvm-svn: 140720

llvm-svn: 140719

llvm-svn: 140718

llvm-svn: 140715

Add llvm-cov skeleton. It has initial support to read coverage info generated by GCOVProfiling.cpp. 
Today, you can do
prompt> clang a.c -ftest-coverage -fprofile-arcs -o a
prompt> ./a
prompt> llvm-cov -gcno a.gcno -gcda a.gcda 
a.c
 :	#include "a.h"
 :	
 :	int main() {
 :		int i = 0;
 :		if (i) {
1:			int j = 0;
1:			j = 1;
1:		} else {
 :			int k = 1;
 :			k = 2;
 :		}
1:		return 0;
 :	}
 :	
 :	

llvm-svn: 140712

llvm-svn: 140709

llvm-svn: 140705

llvm-svn: 140704

llvm-svn: 140703

Handle general Add expressions to avoid leaving around redundant
32-bit IVs.

llvm-svn: 140701

Get rid of some of the no-longer-needed parts of PTXAsmPrinter.

llvm-svn: 140698

Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

llvm-svn: 140697

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696

handling with references to 
http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (r 1.22).

llvm-svn: 140695