There are two conflicting strategies in play:

- Under high register pressure, we want to assign large live ranges
  first. Smaller live ranges are easier to place afterwards.

- Live range splitting is guided by interference, so splitting should be
  deferred until interference is as realistic as possible.

With the recent changes to the live range stages, and with compact
regions enabled, it is less traumatic to split a live range too early.
If some of the split products were too big, they can often be split
again.

By reversing the RS_Split order, we get this queue order:

1. Normal live ranges, large to small.
2. RS_Split live ranges, large to small.

The large-to-small order improves RAGreedy's puzzle solving skills under
high register pressure. It may cause a bit more iterated splitting, but
we handle that better now.

With this change, -compact-regions is mostly an improvement on SPEC.

llvm-svn: 136388

This should be the only code necessary for DWARF EH prepare.

llvm-svn: 136387

llvm-svn: 136375

llvm-svn: 136367

llvm-svn: 136366

Revert r136295.  It broke nightly testers because some parts of codegen weren't aware of the changes to operand ordering.  I hope to revive this sometime in the future, but it's not strictly necessary for now.

llvm-svn: 136362

The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360

identical.

llvm-svn: 136355

llvm-svn: 136341

The new EH is more simple in many respects. Mainly, we don't have to worry about
the "llvm.eh.exception" and "llvm.eh.selector" calls being in weird places.

llvm-svn: 136339

llvm-svn: 136338

landingpad.

llvm-svn: 136329

LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

llvm-svn: 136328

llvm-svn: 136326

* InvokeInst: Get the landingpad instruction associated with this invoke.
* LandingPadInst: A method to reserve extra space for clauses.

llvm-svn: 136325

llvm-svn: 136324

using vextractf128. This will reduce the number of issued instruction
for several avx codes.

llvm-svn: 136323

them to match 256-bit scalar_to_vector+zext.

llvm-svn: 136322

Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

llvm-svn: 136321

a convert pattern close to the instruction definition.

llvm-svn: 136320

llvm-svn: 136319

This takes the new 'resume' instruction and turns it into a direct jump to the
caller's landing pad code. The caller's landingpad instruction is merged with
the landingpad instructions of the callee. This is a bit rough and makes some
assumptions in how the code works. But it passes a simple test.

llvm-svn: 136313

If true and 'model' parameter is not an absolute path, a temp directory will be prepended.
Make it true by default to match current behaviour.

llvm-svn: 136310

Refactor and improve the encodings/decodings for addrmode3 loads, and make the writeback operand always the first.

llvm-svn: 136295

This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292

llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287

Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285

llvm-svn: 136283

llvm-svn: 136278

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277

llvm-svn: 136275

Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274

llvm-svn: 136269

Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264

Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions.  Temporarily XFAIL the asm parsing tests for these instructions.

llvm-svn: 136255

This adds the new instructions 'landingpad' and 'resume'.

llvm-svn: 136253

Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252

llvm-svn: 136250

X86ISD::MEMBARRIER does not require SSE2; it doesn't actually generate any code, and all x86 processors will honor the required semantics.

llvm-svn: 136249

llvm-svn: 136229