TwoAddressInstructionPass should annotate instructions with <undef>
flags when it lower REG_SEQUENCE instructions.  LiveIntervals should not
be in the business of modifying code (except for kill flags, perhaps).

llvm-svn: 141187

llvm-svn: 141184

llvm-svn: 141183

llvm-svn: 141182

llvm-svn: 141178

branch "br i1 %x, label %if_true, label %if_false" then it replaces
"%x" with "true" in places only reachable via the %if_true arm, and
with "false" in places only reachable via the %if_false arm.  Except
that actually it doesn't: if value numbering shows that %y is equal
to %x then, yes, %y will be turned into true/false in this way, but
any occurrences of %x itself are not transformed.  Fix this.  What's
more, it's often the case that %x is an equality comparison such as
"%x = icmp eq %A, 0", in which case every occurrence of %A that is
only reachable via the %if_true arm can be replaced with 0.  Implement
this and a few other variations on this theme.  This reduces the number
of lines of LLVM IR in "GCC as one big file" by 0.2%.  It has a bigger
impact on Ada code, typically reducing the number of lines of bitcode
by around 0.4% by removing repeated compiler generated checks.  Passes
the LLVM nightly testsuite and the Ada ACATS testsuite.

llvm-svn: 141177

it's OK for the false/true destination to have multiple
predecessors as long as the extra ones are dominated by
the branch destination.

llvm-svn: 141176

llvm-svn: 141174

llvm-svn: 141173

it returns false, at least as far as I could tell by reading the code.

llvm-svn: 141172

llvm-svn: 141169

llvm-svn: 141168

llvm-svn: 141166

I noticed during self-review that my previous checkin disabled some
analysis. Even with the reenabled analysis the test case runs in about
5ms. Without the fix, it will take several minutes at least.

llvm-svn: 141164

llvm-svn: 141163

llvm-svn: 141162

Note to compiler writers: never recurse on multiple instruction
operands without memoization.
Fixes rdar://10187945. Was taking 45s, now taking 5ms.

llvm-svn: 141161

llvm-svn: 141158

llvm-svn: 141157

llvm-svn: 141156

Record the registers used and defined by a call in Filler::insertDefsUses.

llvm-svn: 141154

llvm-svn: 141152

filled the last delay slot visited.

llvm-svn: 141151

Filler::findDelayInstr.

llvm-svn: 141150

instructions (instructions that are not NOP).

llvm-svn: 141149

I->getDesc().hasDelaySlot() does.

llvm-svn: 141148

not have to be set.

llvm-svn: 141147

llvm-svn: 141146

the value exceeds that number.

llvm-svn: 141143

This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

llvm-svn: 141142

This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.

llvm-svn: 141140

For example:

  %vreg10:dsub_0<def,undef> = COPY %vreg1
  %vreg10:dsub_1<def> = COPY %vreg2

is rewritten as:

  %D2<def> = COPY %D0, %Q1<imp-def>
  %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def>

The first COPY doesn't care about the previous value of %Q1, so it
doesn't read that register.

The second COPY is a partial redefinition of %Q1, so it implicitly kills
and redefines that register.

This makes it possible to recognize instructions that can harmlessly
clobber the full super-register.  The write and don't read the
super-register.

llvm-svn: 141139

RegisterCoalescer can create sub-register defs when it is joining a
register with a sub-register.  Add <undef> flags to these new
sub-register defs where appropriate.

llvm-svn: 141138

Teach the MC to output code/data region marker labels in MachO and ELF modes.  These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.

llvm-svn: 141135

using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129

llvm-svn: 141125

The <undef> flag says that a MachineOperand doesn't read its register,
or doesn't depend on the previous value of its register.

A full register def never depends on the previous register value.  A
partial register def may depend on the previous value if it is intended
to update part of a register.

For example:

  %vreg10:dsub_0<def,undef> = COPY %vreg1
  %vreg10:dsub_1<def> = COPY %vreg2

The first copy instruction defines the full %vreg10 register with the
bits not covered by dsub_0 defined as <undef>.  It is not considered a
read of %vreg10.

The second copy modifies part of %vreg10 while preserving the rest.  It
has an implicit read of %vreg10.

This patch adds a MachineOperand::readsReg() method to determine if an
operand reads its register.

Previously, this was modelled by adding a full-register <imp-def>
operand to the instruction.  This approach makes it possible to
determine directly from a MachineOperand if it reads its register.  No
scanning of MI operands is required.

llvm-svn: 141124

llvm-svn: 141123

llvm-svn: 141122

llvm-svn: 141118