2-phase build of llvm and llvm-gcc, similar to what the buildbots do, and runs
the regression testsuite.

Things to do:

- Work out some bugs with llvm-gcc flags.
- Not all platforms support ObjC.
- Run the test-suite.

llvm-svn: 113382

so that it can access them.  These are not intended to be externally accessible APIs.

llvm-svn: 113380

llvm-svn: 113378

llvm-svn: 113375

modules are instantiated in them.  If the context is deleted, all of its owned
modules are also deleted.

llvm-svn: 113374

nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.

llvm-svn: 113369

option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).

llvm-svn: 113366

llvm-svn: 113365

Follow the same logic in the LoopPass, ModulePass and CallGraphSCCPass printers,
as it was already used in the BasicBlockPass and FunctionPass printers. This is
more consistent.

The other option would have been to completely disable dumping the analysis
information. However, as this information is the only information printed if the
-analysis flag is set, calling opt would not do anything at all.

llvm-svn: 113360

llvm-svn: 113359

llvm-svn: 113358

Some cases of lowering to rotate were miscompiled.

llvm-svn: 113355

llvm-svn: 113352

llvm-svn: 113350

fixing rdar://8403974

llvm-svn: 113349

implementing rdar://8033482 and PR7254.

llvm-svn: 113348

implementation's job to check for and lex the EndOfStatement
marker.

llvm-svn: 113347

Add this to the mc assembler, fixing PR8061

llvm-svn: 113346

ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.

llvm-svn: 113345

rdar://8061602

llvm-svn: 113343

llvm-svn: 113338

llvm-svn: 113337

related. (attempt deux, complete w/ test update this time)

llvm-svn: 113333

llvm-svn: 113332

llvm-svn: 113331

AliasAnalysis, and some code for implementing the new query on top of
existing implementations by making standard alias and getModRefInfo
queries.

llvm-svn: 113329

present in the function and thus whether aligned load/store instructions can
be used.

llvm-svn: 113323

llvm-svn: 113322

The threshold value of 50 is arbitrary, and I chose it simply by analogy to the inlining thresholds, where
the baseline unrolling threshold is slightly smaller than the baseline inlining threshold.  This could
undoubtedly use some tuning.

llvm-svn: 113306

llvm-svn: 113303

LiveIntervals already adds <imp-def> operands for super-registers when a subreg
def defines the whole register. Thus, it is not necessary to do it again when
rewriting.

In fact, the super-register imp-defs caused miscompilations because the late
scheduler couldn't see that the super-register was read.

We still add super-reg <imp-use,kill> operands when rewriting virtuals to
physicals.

llvm-svn: 113299

register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087

llvm-svn: 113297

llvm-svn: 113293

llvm-svn: 113289

llvm-svn: 113287

Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to

llvm-svn: 113286

llvm-svn: 113285

the provided cleanup function is never actually called.

llvm-svn: 113284

switch to using a ManagedStatic for the global PassRegistry instead of a
ManagedCleanup, and fix a destruction ordering bug this exposed.

llvm-svn: 113283

llvm-svn: 113281