Commits · d1a9d181206c4a614ad36383abf16f5a4ce990cc · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jun 08, 2013
- R600: Use a refined heuristic to choose when switching clause · d1a9d181
  Vincent Lejeune authored Jun 07, 2013
  d1a9d181
- R600: Anti dep better handled in tex clause · 4d143328
  Vincent Lejeune authored Jun 07, 2013
  4d143328
- Remember the anyext patterns. · fdc9d0a9
  Jakob Stoklund Olesen authored Jun 07, 2013
  fdc9d0a9
- Add missing zextloadi1 to i64 patterns. PR16721. · 9f812b97
  Jakob Stoklund Olesen authored Jun 07, 2013
  9f812b97
- Fix an assertion in MemCpyOpt pass. · bd254f26
  Shuxin Yang authored Jun 07, 2013
  bd254f26
- Disallow i64 div/rem in PPC32 counter loops · fa5f6f74
  Hal Finkel authored Jun 07, 2013
  fa5f6f74
- Revert commits related to stack warning. · bd5a201c
  Quentin Colombet authored Jun 07, 2013
  bd5a201c
Jun 07, 2013
- Don't cache the instruction and register info from the TargetMachine, because · 999dacc5
  Bill Wendling authored Jun 07, 2013
  999dacc5
- Don't cache the instruction and register info from the TargetMachine, because · 8f26840c
  Bill Wendling authored Jun 07, 2013
  8f26840c
- Remove unused c'tor. · 52ca447f
  Bill Wendling authored Jun 07, 2013
  52ca447f
- R600: Fix calculation of stack offset in AMDGPUFrameLowering · d7458377
  Tom Stellard authored Jun 07, 2013
  d7458377
- Don't cache the instruction and register info from the TargetMachine, because · 637d97dd
  Bill Wendling authored Jun 07, 2013
  637d97dd
- R600: Rework subtarget info and remove AMDILDevice classes · a6c6e1bf
  Tom Stellard authored Jun 07, 2013
  a6c6e1bf
- Don't cache the instruction and register info from the TargetMachine, because · 6235c06f
  Bill Wendling authored Jun 07, 2013
  6235c06f
- Don't cache the instruction and register info from the TargetMachine, because · 37e9adb0
  Bill Wendling authored Jun 07, 2013
  37e9adb0
- R600: Fix the fetch limits for R600 generation GPUs · 3498e4ff
  Tom Stellard authored Jun 07, 2013
  3498e4ff
- R600: Move Subtarget feature definitions into AMDGPU.td · 99792774
  Tom Stellard authored Jun 07, 2013
  99792774
- R600: Remove unnecessary include · b0804ec2
  Tom Stellard authored Jun 07, 2013
  b0804ec2
- Add a backend option to warn on a given stack size limit. · 6baf581b
  Quentin Colombet authored Jun 07, 2013
  6baf581b
- ARM FastISel integer sext/zext improvements · 06ce03d1
  JF Bastien authored Jun 07, 2013
  06ce03d1
- R600: Don't compare iterators of different maps. · 705d841b
  Benjamin Kramer authored Jun 07, 2013
  705d841b
- Teach AsmPrinter how to print odd constants. · ba366011
  Quentin Colombet authored Jun 07, 2013
  ba366011
- DIBuilder: No functionality change. · 3c6acec0
  Manman Ren authored Jun 07, 2013
  3c6acec0
- Vincent says the element is at most once in the vector, so we don't need a full std::remove. · ebe0be9c
  Benjamin Kramer authored Jun 07, 2013
  ebe0be9c
- Use isxdigit. · 8d477dc0
  Rafael Espindola authored Jun 07, 2013
  8d477dc0
- Fix a typo in asm string of BP* family of instructions. With this fix · 158d8069
  Roman Divacky authored Jun 07, 2013
  158d8069
- Support OpenBSD's native frame protection conventions. · aad6c244
  Rafael Espindola authored Jun 07, 2013
  aad6c244
- R600: Fix a potential iterator invalidation issue. · a857fe11
  Benjamin Kramer authored Jun 07, 2013
  a857fe11
- R600: Remove an extra break in R600OptimizeVectorRegisters.cpp · 931bb768
  Vincent Lejeune authored Jun 07, 2013
  931bb768
- Fold variable that's only used in assert into the assert. · f0ec1994
  Benjamin Kramer authored Jun 07, 2013
  f0ec1994
- Correct wrong register in this example, pointed out by Baoshan Pang. · e0a607e3
  Duncan Sands authored Jun 07, 2013
  e0a607e3
- Don't cache the instruction and register info from the TargetMachine, because · 5e7656bf
  Bill Wendling authored Jun 07, 2013
  5e7656bf
- Don't cache the instruction and register info from the TargetMachine, because · ead89ef6
  Bill Wendling authored Jun 07, 2013
  ead89ef6
- Don't cache the instruction and register info from the TargetMachine, because · f5358213
  Bill Wendling authored Jun 07, 2013
  f5358213
- Don't cache the instruction and register info from the TargetMachine, because · 90bee83c
  Bill Wendling authored Jun 07, 2013
  90bee83c
- Don't cache the instruction and register info from the TargetMachine, because · 4a7a408e
  Bill Wendling authored Jun 07, 2013
  4a7a408e
- [objc-arc] Ensure that the cfg path count does not overflow when we multiply... · 9e7261c8
  Michael Gottesman authored Jun 07, 2013
  9e7261c8
- Don't cache the instruction and register info from the TargetMachine, because · f95178e6
  Bill Wendling authored Jun 07, 2013
  f95178e6
- Don't cache the instruction info and register info objects. · 496dc33b
  Bill Wendling authored Jun 07, 2013
  496dc33b
- DIBuilder: No functionality change. · 60711600
  Manman Ren authored Jun 07, 2013
  60711600