llvm-svn: 174979

Equal treatment of labels and other terminators in MI DAG construction.

MI sched DAG construction allows targets to include terminators into scheduling DAG.
Extend this functionality to labels as well.

llvm-svn: 174977

llvm-svn: 174976

Patch by: Kevin Schoedel

llvm-svn: 174974

instructions.

llvm-svn: 174973

DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.

Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem

llvm-svn: 174972

Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

llvm-svn: 174968

[ASan] Do not use kDefaultShort64bitShadowOffset on Mac, where the binaries may get mapped at 0x100000000+ and thus may interleave with the shadow.

llvm-svn: 174964

'R600/SI: Use proper instructions for array/shadow samplers.' removed two
cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some
shadow array piglit tests with the r600g driver. Reinstating the removed
cases should fix this, and still works with radeonsi as well.

I will follow up with some lit tests which would have caught the regression.

NOTE: This is a candidate for the Mesa stable branch.

Tested-by: Vincent Lejeune <vljn@ovi.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174963

This is based on Bill Wendling's email.  No additional content has been added,
but now there's a place for Attributes to capture future information.

llvm-svn: 174961

llvm-svn: 174959

[asan] change the default mapping offset on x86_64 to 0x7fff8000. This gives roughly 5% speedup. Since this is an ABI change, bump the asan ABI version by renaming __asan_init to __asan_init_v1. llvm part, compiler-rt part will follow

llvm-svn: 174957

llvm-svn: 174955

llvm-svn: 174954

The bitcode writer emits a reference to the attribute group that the object at
the given index refers to. The bitcode reader is modified to read this in and
map it back to the attribute group.

llvm-svn: 174952

llvm-svn: 174950

llvm-svn: 174948

live range after inserting a copy at the end of a block.

llvm-svn: 174945

llvm-svn: 174944

particularly useful for catching issues with architectures that have exotic
terminators like MIPS.

llvm-svn: 174938

llvm-svn: 174937

a critical edge.

llvm-svn: 174936

live ranges should always be extended, and the only successor that should be
considered for extension of other ranges is the target of the split edge.

llvm-svn: 174935

Sorry for the lack of a test case.  I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later.

I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness.

llvm-svn: 174934

A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad
word).

radar://13171406

llvm-svn: 174933

Check for reverse shuffles in the CostModel analysis pass and query
TargetTransform info accordingly. This allows us we can write test cases for
reverse shuffles.

radar://13171406

llvm-svn: 174932

Lower reverse shuffles to a vrev64 and a vext instruction instead of the default
legalization of storing and loading to the stack. This is important because we
generate reverse shuffles in the loop vectorizer when we reverse store to an
array.

  uint8_t Arr[N];
  for (i = 0; i < N; ++i)
    Arr[N - i - 1] = ...

radar://13171760

llvm-svn: 174929

llvm-svn: 174927

Part of rdar://12470373

llvm-svn: 174926

llvm-svn: 174924

Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920

When building the pairable-instruction dependency map, don't search
past the last pairable instruction. For large blocks that have been
divided into multiple instruction groups, searching past the last
instruction in each group is very wasteful. This gives a 32% speedup
on the csa.ll test case from PR15222 (when using 50 instructions
in each group).

No functionality change intended.

llvm-svn: 174915

This map is queried only for instructions in pairs of pairable
instructions; so make sure that only pairs of pairable
instructions are added to the map. This gives a 3.5% speedup
on the csa.ll test case from PR15222.

No functionality change intended.

llvm-svn: 174914

llvm-svn: 174913

MipsCodeEmitter.cpp.

JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not
called when the old JIT is used.

This fixes the following tests which have been failing on
llvm-mips-linux builder:

LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll
LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll
LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll
LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll
LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
LLVM :: ExecutionEngine__hello2.ll
LLVM :: ExecutionEngine__stubs.ll
LLVM :: ExecutionEngine__test-branch.ll
LLVM :: ExecutionEngine__test-call.ll
LLVM :: ExecutionEngine__test-common-symbols.ll
LLVM :: ExecutionEngine__test-loadstore.ll
LLVM :: ExecutionEngine__test-loop.ll

llvm-svn: 174912

llvm-svn: 174911

llvm-svn: 174910

llvm-svn: 174909

llvm-svn: 174907

llvm-svn: 174905