a better solution for it in the future.

llvm-svn: 76818

llvm-svn: 76817

llvm-svn: 76806

llvm-svn: 76803

simplification.
 - NFC

llvm-svn: 76789

llvm-svn: 76786

llvm-svn: 76778

llvm-svn: 76762

llvm-svn: 76750

be placed in the standard data / bss sections.

llvm-svn: 76735

on linux platforms.  The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html 

llvm-svn: 76733

llvm-svn: 76729

Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.

llvm-svn: 76728

llvm-svn: 76727

llvm-svn: 76725

llvm-svn: 76713

assembler / disassembler.

llvm-svn: 76712

llvm-svn: 76711

only caller.

llvm-svn: 76710

updating a mips testcase to expect it.

llvm-svn: 76707

llvm-svn: 76706

a new getSectionForMergableConstant hook.  This removes one dependence
of TAI on Type, and provides the hook with enough info to make the 
right decision based on whether the global has relocations etc.

llvm-svn: 76705

Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.

This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.

llvm-svn: 76703

llvm-svn: 76702

Constant::getRelocationInfo(), which has a much simpler
to use API.  It still should not be part of libvmcore, but
is better than it was.  Also teach it to be smart about 
hidden visibility.

llvm-svn: 76700

negative on an individual bases rather than basing on whether it's in thumb
mode.

llvm-svn: 76698

llvm-svn: 76693

llvm-svn: 76689

virtual.  Just inline it into its two current call sites in preparation
for simplifying the code.

llvm-svn: 76686

llvm-svn: 76683

llvm-svn: 76682

llvm-svn: 76679

pool entry will require relocations against it.  I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.

llvm-svn: 76678

depends on XS1A, but I think the ReadOnlySection is already set up for this
and there is no testcase that this breaks.  If this is really needed, we can
add the appropriate parameterization to TargetAsmInfo in the future to support
this.

llvm-svn: 76667

llvm-svn: 76666

if Xcore doesn't support TLS, it doesn't have to worry about thread local LLVM IR, it should be rejected by a front-end.

llvm-svn: 76665

to twist your brain to see it, I believe it is the same as ELFTargetAsmInfo::SelectSectionForGlobal.

llvm-svn: 76664

llvm-svn: 76662

llvm-svn: 76661

the generic ELF version instead.  This will result in its mergable constant
sections getting named ".rodata.cst4" instead of ".cp.const4", but the
linker looks at the section flags, not the name of the section AFAICT.

llvm-svn: 76659