llvm-svn: 79135

support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127

llvm-svn: 79084

llvm-svn: 79067

llvm-svn: 79039

libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033

llvm-svn: 79032

llvm-svn: 79026

llvm-svn: 79022

llvm-svn: 79014

implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.

llvm-svn: 78995

scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994

target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993

llvm-svn: 78970

llvm-svn: 78968

llvm-svn: 78948

x86_64-apple-darwin10.

--- Reverse-merging r78895 into '.':
U    test/CodeGen/PowerPC/2008-12-12-EH.ll
U    lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U    include/llvm/Target/DarwinTargetAsmInfo.h
U    lib/Target/X86/X86TargetAsmInfo.cpp
U    lib/Target/X86/X86TargetAsmInfo.h
U    lib/Target/ARM/ARMTargetAsmInfo.h
U    lib/Target/ARM/ARMTargetMachine.cpp
U    lib/Target/ARM/ARMTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U    lib/Target/PowerPC/PPCTargetAsmInfo.h
U    lib/Target/PowerPC/PPCTargetMachine.cpp
G    lib/Target/DarwinTargetAsmInfo.cpp

llvm-svn: 78919

llvm-svn: 78918

llvm-svn: 78908

llvm-svn: 78905

llvm-svn: 78904

llvm-svn: 78898

llvm-svn: 78897

to fix it tonight.

llvm-svn: 78896

llvm-svn: 78893

don't need to be exported from the .o files.

llvm-svn: 78892

syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.

llvm-svn: 78890

llvm-svn: 78884

llvm-svn: 78881

PrintUnmangledNameSafely.

llvm-svn: 78878

llvm-svn: 78852

llvm-svn: 78850

llvm-svn: 78848

llvm-svn: 78835

llvm-svn: 78829

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78817

leaving the mayLoad and mayStore settings around only the load/store
instructions where those can't be inferred from the patterns.

llvm-svn: 78815

llvm-svn: 78806

pair instead of from a virtual method on TargetMachine.  This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use 
TargetAsmInfo.

llvm-svn: 78802