by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.

llvm-svn: 114491

llvm-svn: 114490

that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.

llvm-svn: 114489

load when the type of the load is not legal, even if truncates are not free.
The load is going to be legalized to an extending load anyway.

llvm-svn: 114488

llvm-svn: 114487

llvm-svn: 114486

Fixed an issue with the clang type creation code for C++ classes where we wouldn't set a CXXRecordDecl to be NOT empty if we had base classes that were not empty or had virtual functions.

llvm-svn: 114484

llvm-svn: 114483

llvm-svn: 114481

of 'breakpoint command add/list/remove' commands to set breakpoint callbacks,
list them, and then remove one.

Modified the lldbtest.TestBase.expect() method to add two additional keyword
arguments:

o matching (default to True), which, if set to False, reverses the semantics of
  'expect' to 'expect not'

o patterns (default to None), which specifies a list of regexp patterns to match
  against the output from running the command

TestBreakpointCommand.py uses the matching=False and the patterns=[...] expect()
API.

llvm-svn: 114480

If only user of a vreg is an copy instruction to export copy of vreg out of current basic block then insert DBG_VALUE so that debug value of the variable is also transfered to new vreg.
Testcase is in r114476.
This fixes radar 8412415.

llvm-svn: 114478

Correctly register the class extension as the lexical DeclContext for ObjC methods declared with @property in class extensions.
This matches the behavior for setters.

Also pass the class extension to ProcessPropertyDecl as the lexical DeclContext, even when not redeclaring the @property.

This fixes the remaining issues in <rdar://problem/7410145>.

llvm-svn: 114477

llvm-svn: 114476

llvm-svn: 114475

llvm-svn: 114474

the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

llvm-svn: 114473

matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.

llvm-svn: 114472

passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471

llvm-svn: 114470

llvm-svn: 114469

llvm-svn: 114468

Add a warning if no command was attached to the breakpoint.
Update the help slightly.

llvm-svn: 114467

@expectedFailure as of r114384.

llvm-svn: 114466

llvm-svn: 114465

I think I've audited all uses, so it should be dependable for address spaces,
and the pointer+offset info should also be accurate when there.

llvm-svn: 114464

llvm-svn: 114463

llvm-svn: 114461

(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460

llvm-svn: 114459

with missing LHS. radar 8453812. Executable test is checked 
into llvm test suite.

llvm-svn: 114457

For ObjCPropertyDecls in class extensions, use the class extension as the lexical DeclContext for newly created
ObjCMethodDecls.  Further, use the location of the new property declaration as the location of new ObjCMethodDecls
(if they didn't previously exist).

This fixes more of the issues reported in <rdar://problem/7410145>.

llvm-svn: 114456

llvm-svn: 114455

and store intrinsics are represented with MemIntrinsicSDNodes.

llvm-svn: 114454

llvm-svn: 114453

MachinePointerInfo around more.

llvm-svn: 114452

llvm-svn: 114451

llvm-svn: 114450

with an indexed load/store that has an offset in the index.

llvm-svn: 114449

instead of calling lower_bound or upper_bound directly.

This cleans up the search logic a bit because {lower,upper}_bound compare
LR->start by default, and it is usually simpler to search LR->end.

Funnelling all searches through one function also makes it possible to replace
the search algorithm with something faster than binary search.

llvm-svn: 114448

llvm-svn: 114447