Many distros provide stdc++.dll recently. --enable-embed-stdcxx might confuse people.

llvm-svn: 141875

llvm-svn: 141874

llvm-svn: 141873

llvm-svn: 141872

llvm-svn: 141871

This avoids unnecessary expansion of expressions and allows the SCEV
expander to work on expression DAGs, not just trees.
Fixes PR11090.

llvm-svn: 141870

llvm-svn: 141869

just expression trees.

Partially fixes PR11090. Test case will be with the full fix.

llvm-svn: 141868

llvm-svn: 141867

llvm-svn: 141866

Patch by Pekka Jääskeläinen!

llvm-svn: 141865

llvm-svn: 141863

Not having it confused assembly printing of jumptables.

llvm-svn: 141862

attributes are found, propagate them to subsequent declarations.

llvm-svn: 141861

release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859

http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857

Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.

llvm-svn: 141856

llvm-svn: 141855

Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.

llvm-svn: 141854

llvm-svn: 141853

Fix crash-on-invalid, improve error recovery, and test coverage for missing colon after access specifiers in C++

llvm-svn: 141852

llvm-svn: 141851

have the same address as the one we deleted, and we don't want that in the set
yet. Noticed by inspection.

llvm-svn: 141849

down through Module and SymbolVendor into SymbolFile.
Added checks to SymbolFileDWARF that restrict symbol
searches when a namespace is passed in.

llvm-svn: 141847

llvm-svn: 141846

be in namespaces.

llvm-svn: 141845

llvm-svn: 141844

and a "DWARFCompileUnit *" to avoid doing a DIE lookup twice and to prepare
for using namespaces in the lookups.

llvm-svn: 141843

llvm-svn: 141842

llvm-svn: 141840

we don't need to look them up again when materializing.

Switched over the materialization mechanism (for JIT
expressions) and the lookup mechanism (for interpreted
expressions) to use the VariableSP/Symbol that were
found during parsing.

llvm-svn: 141839

file. This will help us to minimize lookups that can't possibly match anything
in the current symbol file.

llvm-svn: 141838

llvm-svn: 141837

Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.

This fixes PR11078.

llvm-svn: 141836

Most instructions have some requirements for their register operands.
Usually, this is expressed as register class constraints in the
MCInstrDesc, but for inline assembly the constraints are encoded in the
flag words.

llvm-svn: 141835

llvm-svn: 141834

The inline asm operand constraint is initially encoded in the virtual
register for the operand, but that register class may change during
coalescing, and the original constraint is lost.

Encode the original register class as part of the flag word for each
inline asm operand.  This makes it possible to recover the actual
constraint required by inline asm, just like we can for normal
instructions.

llvm-svn: 141833

llvm-svn: 141832

llvm-svn: 141831

our current machine instruction defines a register with the same register class
as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it
would ICE because a tail call was expecting one register class but was given
another. (The machine instruction verifier catches this situation.)
<rdar://problem/10270968>

llvm-svn: 141830