Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382

llvm-svn: 147379

python bindinds.
patch by Tom Schuster!

llvm-svn: 147378

llvm-svn: 147373

llvm-svn: 147372

llvm-svn: 147371

Add FMA4 feature flag. Intrinsics coming soon. Also make sse4a feature flag imply sse3. Matches gcc behavior.

llvm-svn: 147370

Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.

llvm-svn: 147369

llvm-svn: 147368

llvm-svn: 147367

Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.

llvm-svn: 147366

llvm-svn: 147365

llvm-svn: 147364

llvm-svn: 147363

llvm-svn: 147362

Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.

llvm-svn: 147361

Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.

llvm-svn: 147360

1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

llvm-svn: 147359

Watch for empty symbol tables by doing a lot more error checking on
all mach-o symbol table load command values and data that is obtained.
This avoids a crash that was happening when there was no string table.

llvm-svn: 147358

'is an extension'. The former is inappropriate and confusing when building with
-Werror/-pedantic-errors.

llvm-svn: 147357

llvm-svn: 147356

llvm-svn: 147355

llvm-svn: 147354

llvm-svn: 147353

llvm-svn: 147352

llvm-svn: 147351

Fixed a crasher that can occur when parsing invalid DWARF.

llvm-svn: 147350

Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.

llvm-svn: 147349

llvm-svn: 147348

llvm-svn: 147347

pointing this out.

llvm-svn: 147346

Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.

llvm-svn: 147345

Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.

llvm-svn: 147344

The exception recovery mechanism for the uninitialized_* algorithms did not work for iterators into discontiguous memory.

llvm-svn: 147343

Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns.

llvm-svn: 147342

llvm-svn: 147341

Add popcnt feature flag to match gcc. This flag is implied when sse42 is enabled, but can be disabled separately. Move popcnt intrinsics to popcntintrin.h to match gcc.

llvm-svn: 147340

Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.

llvm-svn: 147339

llvm-svn: 147338

llvm-svn: 147337