For example:

  %vreg10:dsub_0<def,undef> = COPY %vreg1
  %vreg10:dsub_1<def> = COPY %vreg2

is rewritten as:

  %D2<def> = COPY %D0, %Q1<imp-def>
  %D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def>

The first COPY doesn't care about the previous value of %Q1, so it
doesn't read that register.

The second COPY is a partial redefinition of %Q1, so it implicitly kills
and redefines that register.

This makes it possible to recognize instructions that can harmlessly
clobber the full super-register.  The write and don't read the
super-register.

llvm-svn: 141139

RegisterCoalescer can create sub-register defs when it is joining a
register with a sub-register.  Add <undef> flags to these new
sub-register defs where appropriate.

llvm-svn: 141138

Teach the MC to output code/data region marker labels in MachO and ELF modes.  These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.

llvm-svn: 141135

using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129

llvm-svn: 141125

The <undef> flag says that a MachineOperand doesn't read its register,
or doesn't depend on the previous value of its register.

A full register def never depends on the previous register value.  A
partial register def may depend on the previous value if it is intended
to update part of a register.

For example:

  %vreg10:dsub_0<def,undef> = COPY %vreg1
  %vreg10:dsub_1<def> = COPY %vreg2

The first copy instruction defines the full %vreg10 register with the
bits not covered by dsub_0 defined as <undef>.  It is not considered a
read of %vreg10.

The second copy modifies part of %vreg10 while preserving the rest.  It
has an implicit read of %vreg10.

This patch adds a MachineOperand::readsReg() method to determine if an
operand reads its register.

Previously, this was modelled by adding a full-register <imp-def>
operand to the instruction.  This approach makes it possible to
determine directly from a MachineOperand if it reads its register.  No
scanning of MI operands is required.

llvm-svn: 141124

llvm-svn: 141116

When resolving an operator list element reference, resolve all
operator operands and try to fold the operator first.  This allows the
operator to collapse to a list which may then be indexed.

Before, it was not possible to do this:
class D<int a, int b> { ... }
class C<list<int> A> : D<A[0], A[1]>;
class B<list<int> b> : C<!foreach(...,b)>;

Now it is.

llvm-svn: 141101

llvm-svn: 141097

Put GCOVFile and other related interface in a common header so that llvm-cov tool can share it with GCOV writer.

llvm-svn: 141095

llvm-svn: 141093

This has already been done for most other targets.

llvm-svn: 141083

This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.

The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs.  However, you may preprocess an td
input (and only preprocess it).

To test the proprecessor, type:
  tblgen -E -o $@ $<

llvm-svn: 141079

llvm-svn: 141075

Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074

llvm-svn: 141066

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"

llvm-svn: 141059

llvm-svn: 141058

llvm-svn: 141057

llvm-svn: 141050

llvm-svn: 141046

llvm-svn: 141043

Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.

llvm-svn: 141042

llvm-svn: 141040

llvm-svn: 141038

llvm-svn: 141032

This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.

llvm-svn: 141031

llvm-svn: 141029

llvm-svn: 141028

Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.

llvm-svn: 141026

llvm-svn: 141025

llvm-svn: 141024

llvm-svn: 141023

It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

llvm-svn: 141020

registers.

llvm-svn: 141019

llvm-svn: 141017

registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015

Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.

llvm-svn: 141007

llvm-svn: 141005