The old code would look at kills and defs in one pass over the
instruction operands, causing problems with this code:

  %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg
  %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg

The last instruction kills and redefines %R0, so it is still live after
the instruction.

This caused a register scavenger crash when compiling 483.xalancbmk for
armv6. I am not including a test case because it requires too much bad
luck to expose this old bug.

First you need to convince the register allocator to use %R0 twice on
the tADDrr instruction, then you have to convince BranchFolding to do
something that causes it to run the register scavenger on he bad block.

<rdar://problem/9898200>

llvm-svn: 136973

The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969

llvm-svn: 136968

<rdar://problem/9878189>

llvm-svn: 136962

llvm-svn: 136956

llvm-svn: 136954

inlined variable, based on the discussion in PR10542.

This explodes the runtime of several passes down the pipeline due to
a large number of "copies" remaining live across a large function. This
only shows up with both debug and opt, but when it does it creates
a many-minute compile when self-hosting LLVM+Clang. There are several
other cases that show these types of regressions.

All of this is tracked in PR10542, and progress is being made on fixing
the issue. Once its addressed, the re-instated, but until then this
restores the performance for self-hosting and other opt+debug builds.

Devang, let me know if this causes any trouble, or impedes fixing it in
any way, and thanks for working on this!

llvm-svn: 136953

llvm-svn: 136942

Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940

Patch by Ivan Krasin!

llvm-svn: 136921

llvm-svn: 136916

llvm-svn: 136915

We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped.

llvm-svn: 136910

llvm-svn: 136909

llvm-svn: 136908

This is meant to be overriden by backends. Implement an override on PowerPC
which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes
a commented out hack and enables hello world to be compiled on PowerPC.

llvm-svn: 136905

llvm-svn: 136901

llvm-svn: 136900

llvm-svn: 136899

LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets.  Add an appropriate immediate type for them.

llvm-svn: 136896

llvm-svn: 136884

logic moved over to its own enum.  Noticed by Andrey Karpov with
the PVS-studio tool.

llvm-svn: 136881

llvm-svn: 136880

the PVS-studio tool.

llvm-svn: 136878

llvm-svn: 136877

llvm-svn: 136875

llvm-svn: 136874

llvm-svn: 136873

llvm-svn: 136872

llvm-svn: 136871

llvm-svn: 136870

llvm-svn: 136869

llvm-svn: 136868

llvm-svn: 136867

llvm-svn: 136866

reported at http://habrahabr.ru/blogs/compilers/125626/.

llvm-svn: 136865

llvm-svn: 136857

Move the reloc size assert into AsmBackend - where it is more apropos.

llvm-svn: 136855

Fixes PR10527.

llvm-svn: 136853

Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845