1. Remove a bunch of ifdef'd code.
2. When a block just contains an uncond branch, change all blocks branching
   to it to jump to the destination instead.
3. If branch analysis tells us some edges in the machinecfg are not actually
   possible, remove them.

#2 triggers a suprisingly large number of times.

llvm-svn: 31094

This is currently disabled by default and limited in several ways, but does
have a positive effect.

llvm-svn: 31090

llvm-svn: 31088

output.

llvm-svn: 31067

This patch implements the first increment for the Signless Types feature.
All changes pertain to removing the ConstantSInt and ConstantUInt classes
in favor of just using ConstantInt.

llvm-svn: 31063

blocks into the basic block list when lowering the switch inst. into a
binary tree of if-then statements. This allows the "visitSwitchCase" func
to allow for fall-through behavior.

llvm-svn: 31057

llvm-svn: 31040

llvm-svn: 31035

# notes in it.

llvm-svn: 31026

llvm-svn: 31025

one separately.

llvm-svn: 31022

llvm-svn: 31020

llvm-svn: 31019

llvm-svn: 31017

llvm-svn: 31016

llvm-svn: 31009

branch folding can now compile stuff like this:

void foo(int W, int X, int Y, int Z) {
  if (W & 1) {
    for (; X;--X) bar();
  } else if (W & 2) {
    for (; Y;--Y) bar();
  } else if (W & 4) {
    for (; Z;--Z) bar();
  } else if (W & 8) {
    for (; W;--W) bar();
  }

  if (W) {
    bar();
  }
}

contrived testcase where loops exits all end up merging together.  To have
the loop merges be:

...
        cmplw cr0, r30, r27
        bne cr0, LBB1_14        ;bb38
LBB1_16:        ;cond_next48.loopexit
        mr r27, r29
LBB1_20:        ;cond_next48
        cmplwi cr0, r27, 0
        beq cr0, LBB1_22        ;UnifiedReturnBlock
...

instead of:


...
        cmplw cr0, r30, r27
        bne cr0, LBB1_14        ;bb38
LBB1_16:        ;cond_next48.loopexit
        mr r27, r29
        b LBB1_20       ;cond_next48
LBB1_17:        ;cond_next48.loopexit1
        b LBB1_20       ;cond_next48
LBB1_18:        ;cond_next48.loopexit2
        b LBB1_20       ;cond_next48
LBB1_19:        ;cond_next48.loopexit3
LBB1_20:        ;cond_next48
        cmplwi cr0, r27, 0
        beq cr0, LBB1_22        ;UnifiedReturnBlock
...


This is CodeGen/PowerPC/branch-opt.ll

llvm-svn: 31006

llvm-svn: 31001

It now correctly deletes unreachable blocks and blocks that are empty.

llvm-svn: 31000

llvm-svn: 30999

llvm-svn: 30997

(vector_shuffle
  (vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
  (undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
  vbitconvert
is a very bad idea.

llvm-svn: 30989

llvm-svn: 30984

llvm-svn: 30982

llvm-svn: 30961

llvm-svn: 30959

so that it can be deleted if unused.

llvm-svn: 30955

llvm-svn: 30953

SelectionDAG and it has since bitrotted.  Remove the copy from SelectionDAG.
Next, remove the constant folding piece of DAGCombiner::SimplifySetCC into
a new FoldSetCC method which can be used by getNode() and SimplifySetCC.

This fixes obscure bugs.

llvm-svn: 30952

llvm-svn: 30951

llvm-svn: 30950

llvm-svn: 30948

which is undefined.  "0" isn't a power of 2.

llvm-svn: 30947

llvm-svn: 30945

it just deletes empty MBB's.  Soon it will do more :)

llvm-svn: 30941

llvm-svn: 30939

llvm-svn: 30927

llvm-svn: 30926

apply to rems as well as divs.  This fixes PR945 and speeds up ReedSolomon
from 14.57s to 10.90s (which is now faster than gcc).

It compiles CodeGen/X86/rem.ll into:

_test1:
        subl $4, %esp
        movl %esi, (%esp)
        movl $2155905153, %ecx
        movl 8(%esp), %esi
        movl %esi, %eax
        imull %ecx
        addl %esi, %edx
        movl %edx, %eax
        shrl $31, %eax
        sarl $7, %edx
        addl %eax, %edx
        imull $255, %edx, %eax
        subl %eax, %esi
        movl %esi, %eax
        movl (%esp), %esi
        addl $4, %esp
        ret
_test2:
        movl 4(%esp), %eax
        movl %eax, %ecx
        sarl $31, %ecx
        shrl $24, %ecx
        addl %eax, %ecx
        andl $4294967040, %ecx
        subl %ecx, %eax
        ret
_test3:
        subl $4, %esp
        movl %esi, (%esp)
        movl $2155905153, %ecx
        movl 8(%esp), %esi
        movl %esi, %eax
        mull %ecx
        shrl $7, %edx
        imull $255, %edx, %eax
        subl %eax, %esi
        movl %esi, %eax
        movl (%esp), %esi
        addl $4, %esp
        ret

instead of div/idiv instructions.

llvm-svn: 30920

llvm-svn: 30916