changing the interface to allow for future changes.

llvm-svn: 41384

llvm-svn: 41360

llvm-svn: 41359

llvm-svn: 41319

llvm-svn: 41318

llvm-svn: 41284

llvm-svn: 41225

llvm-svn: 41224

llvm-svn: 41208

 *) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179

llvm-svn: 41178

MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161

llvm-svn: 41160

llvm-svn: 41159

fixed to generate instructions (add, lui) glued!

llvm-svn: 41158

Newline added after macros at function init on generated asm!

llvm-svn: 41157

llvm-svn: 41156

llvm-svn: 41155

llvm-svn: 41154

Added InsertNoop support

llvm-svn: 41153

MipsAdd opcode added

llvm-svn: 41152

Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151

llvm-svn: 41150

llvm-svn: 41149

hard to catch bugs with retaddr lowering

llvm-svn: 41104

llvm-svn: 41103

llvm-svn: 41059

see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049

llvm-svn: 41048

llvm-svn: 41021

able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020

Make a 'memop' pattern just for them.

llvm-svn: 41017

llvm-svn: 41013

Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).

llvm-svn: 41010

llvm-svn: 41009

Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

llvm-svn: 41007

llvm-svn: 40986

llvm-svn: 40985

llvm-svn: 40982

llvm-svn: 40973