ISD node.  The only change in the generated isel code are comments
like:

<                 // Src: (X86dec_flag:i16 GR16:i16:$src)
---
>                 // Src: (X86dec_flag:i16:i32 GR16:i16:$src)

because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case.  Wewt.

llvm-svn: 99369

llvm-svn: 99360

llvm-svn: 99359

llvm-svn: 99358

test run permformance numbers say as to whether it helps.

llvm-svn: 99355

This reverts commit 99345. It was breaking buildbots.

llvm-svn: 99352

llvm-svn: 99350

llvm-svn: 99348

just use an empty result list.

llvm-svn: 99346

This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.

llvm-svn: 99345

llvm-svn: 99344

for the noinline attribute, and make the inliner refuse to
inline a call site when the call site is marked noinline even
if the callee isn't.  This fixes PR6682.

llvm-svn: 99341

needed here.

llvm-svn: 99339

beyond just calling getTypeToTransformTo.

llvm-svn: 99335

for ignoring debug info intrinsics everywhere else is to advance
past them, and it needs to be consistent.

llvm-svn: 99332

patch by Alex Mac!

llvm-svn: 99330

llvm-svn: 99328

llvm-svn: 99327

Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326

llvm-svn: 99324

llvm-svn: 99322

llvm-svn: 99321

Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

llvm-svn: 99320

llvm-svn: 99319

These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309

llvm-svn: 99295

Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288

Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.

llvm-svn: 99282

if Function::hasAddressTaken works as advertised

also included some cosmetic cleanups

llvm-svn: 99276

llvm-svn: 99275

llvm-svn: 99266

of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265

llvm-svn: 99263

of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261

Also, both MCMachOStreamer and MCAssembler are now target independent!

llvm-svn: 99256

MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.

llvm-svn: 99249

MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.

llvm-svn: 99248

llvm-svn: 99245

MC: Tweak MCInstFragment to include the encoded data and fixups, so that we don't need to recompute them during relaxation. I will revisit this once all the other pieces of fast relaxation are in place.

llvm-svn: 99244

llvm-svn: 99231