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  1. Sep 19, 2013
    • Andrew Trick's avatar
      whitespace · dc073add
      Andrew Trick authored
      llvm-svn: 190973
      dc073add
    • Reed Kotler's avatar
      Fix two issues regarding Got pointer (GP) setup. · d6aadc79
      Reed Kotler authored
      1) make sure that the first two instructions of the sequence cannot
      separate from each other. The linker requires that they be sequential.
      If they get separated, it can still work but it will not work in all
      cases because the first of the instructions mostly involves the hi part
      of the pc relative offset and that part changes slowly. You would have
      to be at the right boundary for this to matter.
      2) make sure that this sequence begins  on a longword boundary. 
      There appears to be a bug in binutils which makes some of these calculations
      get messed up if the instruction sequence does not begin on a longword
      boundary. This is being investigated with the appropriate binutils folks.
      
      llvm-svn: 190966
      d6aadc79
    • Adrian Prantl's avatar
      Debug info: Get rid of the VLA indirection hack in FastISel. · 262bcf45
      Adrian Prantl authored
      Use the DIVariable::isIndirect() flag set by the frontend instead of
      guessing whether to set the machine location's indirection bit.
      Paired commit with CFE.
      
      llvm-svn: 190961
      262bcf45
  2. Sep 18, 2013
  3. Sep 17, 2013
    • Reid Kleckner's avatar
      COFF: Emit all MCSymbols rather than filtering out some of them · 3ea536fe
      Reid Kleckner authored
      In particular, this means we emit non-external symbols defined to
      variables, such as aliases or absolute addresses.
      
      This is needed to implement /safeseh, and it appears there was some
      confusion about what symbols to emit previously.
      
      llvm-svn: 190888
      3ea536fe
    • Reid Kleckner's avatar
      COFF: Remove ExportSection, which has been dead since r114823 · 50689eb9
      Reid Kleckner authored
      llvm-svn: 190887
      50689eb9
    • Eric Christopher's avatar
      Move variable into assert to avoid unused variable warning. · e7af7bd8
      Eric Christopher authored
      llvm-svn: 190886
      e7af7bd8
    • Matt Arsenault's avatar
      Cleanup handling of constant function casts. · e6952f28
      Matt Arsenault authored
      Some of this code is no longer necessary since int<->ptr casts are no
      longer occur as of r187444.
      
      This also fixes handling vectors of pointers, and adds a bunch of new
      testcases for vectors and address spaces.
      
      llvm-svn: 190885
      e6952f28
    • Bill Schmidt's avatar
      [PowerPC] Add a FIXME. · bdae03f2
      Bill Schmidt authored
      Documenting a design choice to generate only medium model sequences for TLS
      addresses at this time.  Small and large code models could be supported if
      necessary.
      
      llvm-svn: 190883
      bdae03f2
    • Bill Schmidt's avatar
      [PowerPC] Fix problems with large code model (PR17169). · bb381d70
      Bill Schmidt authored
      Large code model on PPC64 requires creating and referencing TOC entries when
      using the addis/ld form of addressing.  This was not being done in all cases.
      The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this.  Two
      test cases are also modified to reflect this requirement.
      
      Fast-isel was not creating correct code for loading floating-point constants
      using large code model.  This also requires the addis/ld form of addressing.
      Previously we were using the addis/lfd shortcut which is only applicable to
      medium code model.  One test case is modified to reflect this requirement.
      
      llvm-svn: 190882
      bb381d70
    • Arnold Schwaighofer's avatar
      Costmodel: Add support for horizontal vector reductions · cae8735a
      Arnold Schwaighofer authored
      Upcoming SLP vectorization improvements will want to be able to estimate costs
      of horizontal reductions. Add infrastructure to support this.
      
      We model reductions as a series of (shufflevector,add) tuples ultimately
      followed by an extractelement. For example, for an add-reduction of <4 x float>
      we could generate the following sequence:
      
       (v0, v1, v2, v3)
         \   \  /  /
           \  \  /
             +  +
      
       (v0+v2, v1+v3, undef, undef)
          \      /
       ((v0+v2) + (v1+v3), undef, undef)
      
       %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
                                 <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
       %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
       %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
                                <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
       %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
       %r = extractelement <4 x float> %bin.rdx8, i32 0
      
      This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)"
      that will allow clients to ask for the cost of such a reduction (as backends
      might generate more efficient code than the cost of the individual instructions
      summed up). This interface is excercised by the CostModel analysis pass which
      looks for reduction patterns like the one above - starting at extractelements -
      and if it sees a matching sequence will call the cost model interface.
      
      We will also support a second form of pairwise reduction that is well supported
      on common architectures (haddps, vpadd, faddp).
      
       (v0, v1, v2, v3)
        \   /    \  /
       (v0+v1, v2+v3, undef, undef)
          \     /
       ((v0+v1)+(v2+v3), undef, undef, undef)
      
        %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
              <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
        %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
              <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
        %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
        %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
              <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
        %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
              <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
        %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
        %r = extractelement <4 x float> %bin.rdx.1, i32 0
      
      llvm-svn: 190876
      cae8735a
    • Arnold Schwaighofer's avatar
      SLPVectorizer: Don't vectorize phi nodes that use invoke values · 4a3dcaa1
      Arnold Schwaighofer authored
      We can't insert an insertelement after an invoke. We would have to split a
      critical edge. So when we see a phi node that uses an invoke we just give up.
      
      radar://14990770
      
      llvm-svn: 190871
      4a3dcaa1
    • Quentin Colombet's avatar
      [InstCombiner] Slice a big load in two loads when the elements are next to each · b8d672ef
      Quentin Colombet authored
      other in memory.
      
      The motivation was to get rid of truncate and shift right instructions that get
      in the way of paired load or floating point load.
      E.g.,
      Consider the following example:
      struct Complex {
        float real;
        float imm;
      };
      
      When accessing a complex, llvm was generating a 64-bits load and the imm field
      was obtained by a trunc(lshr) sequence, resulting in poor code generation, at
      least for x86.
      
      The idea is to declare that two load instructions is the canonical form for
      loading two arithmetic type, which are next to each other in memory.
      
      Two scalar loads at a constant offset from each other are pretty
      easy to detect for the sorts of passes that like to mess with loads. 
      
      <rdar://problem/14477220>
      
      llvm-svn: 190870
      b8d672ef
    • Preston Gurd's avatar
      Remove unused code, which had been commented out. · ba6f9d1b
      Preston Gurd authored
      llvm-svn: 190869
      ba6f9d1b
    • Serge Pavlov's avatar
      Added documentation to getMemsetStores. · 8ec39992
      Serge Pavlov authored
      llvm-svn: 190866
      8ec39992
    • Ben Langmuir's avatar
      Add llvm.x86.* intrinsics for Intel SHA Extensions · de39520f
      Ben Langmuir authored
      Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as
      well as tests. Also remove mayLoad and hasSideEffects, which can be inferred
      from the instruction patterns.
      
      llvm-svn: 190864
      de39520f
    • Kostya Serebryany's avatar
      [asan] inline the calls to __asan_stack_free_* with small sizes. Yet another... · bc86efb8
      Kostya Serebryany authored
      [asan] inline the calls to __asan_stack_free_* with small sizes. Yet another 10%-20% speedup for use-after-return
      
      llvm-svn: 190863
      bc86efb8
    • Joey Gouly's avatar
      830c27ab
    • Stepan Dyatkovskiy's avatar
      Bugfix for PR17099: · dc2c4b44
      Stepan Dyatkovskiy authored
      Wrong cast operation.
      MergeFunctions emits Bitcast instead of pointer-to-integer operation.
      Patch fixes MergeFunctions::writeThunk function. It replaces
      unconditional Bitcast creation with "Value* createCast(...)" method, that
      checks operand types and selects proper instruction.
      See unit-test as example.
      
      llvm-svn: 190859
      dc2c4b44
    • Elena Demikhovsky's avatar
      AVX-512: Converted to Unix style · ac3e8eb9
      Elena Demikhovsky authored
      llvm-svn: 190851
      ac3e8eb9
    • Craig Topper's avatar
      Add AES and SHA instructions to the load folding tables. · 514f02cc
      Craig Topper authored
      llvm-svn: 190850
      514f02cc
    • Craig Topper's avatar
      Fix column alignment. No functional change. · 684abc82
      Craig Topper authored
      llvm-svn: 190849
      684abc82
    • Kevin Qin's avatar
      Implement 3 AArch64 neon instructions : umov smov ins. · 36399e6b
      Kevin Qin authored
      llvm-svn: 190839
      36399e6b
    • Quentin Colombet's avatar
      [SelectionDAG] Teach the vector scalarizer about TRUNCATE. · d30a9585
      Quentin Colombet authored
      When a truncate node defines a legal vector type but uses an illegal
      vector type, the legalization process was splitting the vector until
      <1 x vector> type, but then it was failing to scalarize the node because
      it did not know how to handle TRUNCATE.
      
      <rdar://problem/14989896>
      
      llvm-svn: 190830
      d30a9585
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