llvm-svn: 107234

llvm-svn: 107233

Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree. 

llvm-svn: 107228

InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.

This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.

llvm-svn: 107227

llvm-svn: 107225

where each loop's induction variable's start value is the exit
value of a preceding loop.

llvm-svn: 107224

llvm-svn: 107215

llvm-svn: 107214

llvm-svn: 107213

llvm-svn: 107211

llvm-svn: 107208

llvm-svn: 107206

metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

llvm-svn: 107205

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

Inspired by Artur Pietrek.

llvm-svn: 107202

llvm-svn: 107201

A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.

This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.

llvm-svn: 107193

The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.

llvm-svn: 107189

llvm-svn: 107178

llvm-svn: 107175

llvm-svn: 107168

The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

llvm-svn: 107167

llvm-svn: 107166

llvm-svn: 107154

a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

llvm-svn: 107147

llvm-svn: 107145

is stripped off.  Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.

llvm-svn: 107142

llvm-svn: 107141

of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

llvm-svn: 107140

to unsigned only to extend back to a pointer sized value on the
next line.

llvm-svn: 107139

ignored!  Remove it.

llvm-svn: 107138

but then not actually used - maybe a bug?  Remove the variable.

llvm-svn: 107137

llvm-svn: 107136

llvm-svn: 107135

and thumb_mode.

llvm-svn: 107133

llvm-svn: 107132

llvm-svn: 107131

llvm-svn: 107130

in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.

llvm-svn: 107129

llvm-svn: 107128