This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411
llvm-svn: 156599

llvm-svn: 156597

Modified the symbolication.Image object to store its uuid as a uuid.UUID object and made an accessor for getting a normalized UUID value out of the image object.

Modified the crashlog darwin module to always create a uuid.UUID object when making the symbolication.Image objects. Also modified it to handle some more types of crash log files and improved the register reading for thread registers of crashed threads.

llvm-svn: 156596

Don't intercept the quit command and override what is was doing. This was causing the "lldb" command line to deadlock when the quit command was executed sometimes.

llvm-svn: 156595

but it generates int3 on x86 instead of ud2.

llvm-svn: 156593

compilers and expected defaults.

Part of rdar://11325849

llvm-svn: 156592

to user only read/write.

Part of rdar://11325849

llvm-svn: 156591

llvm-svn: 156589

"--stack-history" now works if you have MallocStackLogggingNoCompact defined in your app's environment.

llvm-svn: 156588

The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

llvm-svn: 156587

llvm-svn: 156586

add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

llvm-svn: 156585

Added the ability to get the stack history for a malloc block. This is a work in progress. Checking this in so I can work on it some more.

llvm-svn: 156584

numberWithBool:/numberWithInteger:/numberWithUnsignedInteger: NSNumber selectors.

rdar://11428703

llvm-svn: 156583

llvm-svn: 156582

rdar://problem/11428134

llvm-svn: 156581

a horrible bug in GetLazyBindings where we falsely appended a field suffix when traversing 3 or more
layers of lazy bindings.  I don't have a reduced test case yet; but I have added the original source
to an internal regression test suite.  I'll see about coming up with a reduced test case.

Fixes <rdar://problem/11405978> (for real).

llvm-svn: 156580

llvm-svn: 156579

to reason about.

As part of taint propagation, we now allow creation of non-integer
symbolic expressions like a cast from int to float.

Addresses PR12511 (radar://11215362).

llvm-svn: 156578

Patch by Jack Carter.

llvm-svn: 156577

llvm-svn: 156576

llvm-svn: 156575

Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.
llvm-svn: 156574

llvm-svn: 156573

llvm-svn: 156572

llvm-svn: 156571

to complete C++ classes before traversing their base
classes.

llvm-svn: 156570

llvm-svn: 156569

llvm-svn: 156568

llvm-svn: 156567

rdar://11426994

llvm-svn: 156565

llvm-svn: 156564

Sanity check the return value from SBSCopyApplicationDisplayIdentifiers() before calling CFArrayGetCount() on it.

rdar://problem/11331867

llvm-svn: 156562

Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

llvm-svn: 156561

llvm-svn: 156560

llvm-svn: 156559

llvm-svn: 156558

Fixes assertion hit in the preprocessing record. rdar://11426523

llvm-svn: 156557

This commit broke an external linux bot and gave a compile-time warning.

llvm-svn: 156556

The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

llvm-svn: 156555