aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901

in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857

calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856

which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855

"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831

directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830

llvm-svn: 117824

llvm-svn: 117823

llvm-svn: 117822

llvm-svn: 117821

for shl.  Caught by inspection.

llvm-svn: 117820

llvm-svn: 117819

llvm-svn: 117818

llvm-svn: 117817

llvm-svn: 117816

just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815

llvm-svn: 117785

llvm-svn: 117773

Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.

llvm-svn: 117667

Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514

llvm-svn: 117485

llvm-svn: 117474

(still to add ud2b).

llvm-svn: 117435

the wait prefix).

llvm-svn: 117434

sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433

will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427

memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413

llvm-svn: 117378

on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364

cannot use tailcall.  PR 8461.

llvm-svn: 117322

we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241

llvm-svn: 117206

llvm-svn: 117205

llvm-svn: 117202

until other LLVM projects using these are cleaned up.

llvm-svn: 117200

llvm-svn: 117099