Commits · dd52d58680d796f85394eb72e6d2a2182145cce7 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Aug 01, 2013
- Temporarily xfail a test that breaks on OS X when building with LTO. · dd52d586
  Bob Wilson authored Aug 01, 2013
  dd52d586
- Bugfix for making the DWARF debug strings and labels to code emitted as... · afcc6202
  Carlo Kok authored Aug 01, 2013
  afcc6202
- R600: Add 64-bit float load/store support · 0344cdfe
  Tom Stellard authored Aug 01, 2013
  0344cdfe
- R600: Use 64-bit alignment for 64-bit kernel arguments · 53698938
  Tom Stellard authored Aug 01, 2013
  53698938
- R600/SI: Custom lower i64 ZERO_EXTEND · 98f675a9
  Tom Stellard authored Aug 01, 2013
  98f675a9
- EVEX and compressed displacement encoding for AVX512 · b1266b54
  Elena Demikhovsky authored Aug 01, 2013
  b1266b54
- [SystemZ] Reuse CC results for integer comparisons with zero · fd7f4ae6
  Richard Sandiford authored Aug 01, 2013
  fd7f4ae6
- [SystemZ] Prefer comparisons with zero · a075708a
  Richard Sandiford authored Aug 01, 2013
  a075708a
- Add tests for Mips DSP instructions. · deaa618c
  Vladimir Medic authored Aug 01, 2013
  deaa618c
- AArch64: add initial NEON support · 40e9efd7
  Tim Northover authored Aug 01, 2013
  40e9efd7
- XCore target: Fix Vararg handling · 4be00f8a
  Robert Lytton authored Aug 01, 2013
  4be00f8a
- XCore target: Add byval handling · 4e60a3f4
  Robert Lytton authored Aug 01, 2013
  4e60a3f4
- Xcore target · b4787a15
  Robert Lytton authored Aug 01, 2013
  b4787a15
- Fix some misc. issues with Mips16 fp stubs. · 302ae6b0
  Reed Kotler authored Aug 01, 2013
  302ae6b0
Jul 31, 2013
- Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. · 78f9572f
  Kevin Enderby authored Jul 31, 2013
  78f9572f
- Revert "R600: Non vector only instruction can be scheduled on trans unit" · ca69a53b
  Tom Stellard authored Jul 31, 2013
  ca69a53b
- R600: Avoid more than 4 literals in the same instruction group at scheduling · bb3f9311
  Vincent Lejeune authored Jul 31, 2013
  bb3f9311
- R600: Non vector only instruction can be scheduled on trans unit · df18804e
  Vincent Lejeune authored Jul 31, 2013
  df18804e
- Reject bitcasts between address spaces with different sizes · 24b49c41
  Matt Arsenault authored Jul 31, 2013
  24b49c41
- [SystemZ] Implement isLegalAddressingMode() · 791bea41
  Richard Sandiford authored Jul 31, 2013
  791bea41
- [SystemZ] Be more careful about inverting CC masks (conditional loads) · ee834382
  Richard Sandiford authored Jul 31, 2013
  ee834382
- [SystemZ] Be more careful about inverting CC masks · 3d768e33
  Richard Sandiford authored Jul 31, 2013
  3d768e33
- [SystemZ] Move compare-and-branch generation even later · 8a757bba
  Richard Sandiford authored Jul 31, 2013
  8a757bba
- [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress() · 6a06ba36
  Richard Sandiford authored Jul 31, 2013
  6a06ba36
- Added INSERT and EXTRACT intructions from AVX-512 ISA. · 67b05fc0
  Elena Demikhovsky authored Jul 31, 2013
  67b05fc0
- [SystemZ] Add RISBLG and RISBHG instruction definitions · 6cf80b3e
  Richard Sandiford authored Jul 31, 2013
  6cf80b3e
- Changed register names (and pointer keywords) to be lower case when using... · efd67d46
  Craig Topper authored Jul 31, 2013
  efd67d46
- Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y). · c7be519d
  Owen Anderson authored Jul 30, 2013
  c7be519d
Jul 30, 2013
- isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add instructions · b7d5409a
  David Majnemer authored Jul 30, 2013
  b7d5409a
- Change behavior of calling bitcasted alias functions. · cacbb237
  Matt Arsenault authored Jul 30, 2013
  cacbb237
- This test may have been sensitive to the ARM ABI... · 3f423dec
  Andrew Trick authored Jul 30, 2013
  3f423dec
- MI Sched fix: assert "Disconnected LRG within the scheduling region." · d9761776
  Andrew Trick authored Jul 30, 2013
  d9761776
- R600/SI: Expand vector fp <-> int conversions · aa313d0a
  Tom Stellard authored Jul 30, 2013
  aa313d0a
- This patch implements parsing of mips FCC register operands. The example... · 643b3987
  Vladimir Medic authored Jul 30, 2013
  643b3987
- [ARM] check bitwidth in PerformORCombine · 0c2ee5a2
  Saleem Abdulrasool authored Jul 30, 2013
  0c2ee5a2
- [R600] Replicate old DAGCombiner behavior in target specific DAG combine. · e2e0548d
  Quentin Colombet authored Jul 30, 2013
  e2e0548d
- [DAGCombiner] insert_vector_elt: Avoid building a vector twice. · 6bf4baa4
  Quentin Colombet authored Jul 30, 2013
  6bf4baa4
- Move file to X86 and add a triple to fix darwin bots for now. · 4ed04e2e
  Eric Christopher authored Jul 30, 2013
  4ed04e2e
- Fix a truly egregious thinko in anonymous namespace check, · e414ece7
  Eric Christopher authored Jul 29, 2013
  e414ece7
- Make sure we don't emit an ODR hash for types with no name and make · d853ea31
  Eric Christopher authored Jul 29, 2013
  d853ea31