llvm-svn: 132718

llvm-svn: 132717

Requested by nbjoerg!

llvm-svn: 132716

llvm-svn: 132715

llvm-svn: 132711

-undef flag is passed in. Also __ASSEMBLER__ with -x assembler-with-cpp. (Don't
ask.)

llvm-svn: 132708

Switched to DenseMap for allowed sets in PBQP. Reduces total LLC time by 15% on CINT2006 for x86-32.

llvm-svn: 132707

codegen. Thanks Galina.

llvm-svn: 132706

specializations within an explicit instantiation to default to off
(enabled by -pedantic). Nobody else seem to implement C++
[temp.explicit]p3. Fixes PR10093.

llvm-svn: 132704

Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:

- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703

I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.

llvm-svn: 132701

llvm-svn: 132700

rdar://problem/9556069

llvm-svn: 132699

When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.

This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.

llvm-svn: 132697

load.  rdar://problem/6373334

llvm-svn: 132696

Add -O1/2/3 to bugpoint, so when you conclude opt -O2 reproduces an issue, you can just run bugpoint -O2. :)  My implementation isn't precisely equivalent to what opt does, but as far as I can tell, it's close enough.

llvm-svn: 132695

llvm-svn: 132694

llvm-svn: 132693

llvm-svn: 132692

llvm-svn: 132691

Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.

This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.

llvm-svn: 132690

legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.

llvm-svn: 132689

llvm-svn: 132687

it was added, the test has regressed, so XFAIL it.

llvm-svn: 132686

llvm-svn: 132682

llvm-svn: 132681

The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.

When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.

We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.

llvm-svn: 132680

llvm-svn: 132679

llvm-svn: 132678

specializing a member of an unspecialized template, and recover from
such errors without crashing. Fixes PR10024 / <rdar://problem/9509761>.

llvm-svn: 132677

llvm-svn: 132676

llvm-svn: 132675

"unsafe mix of type 'int' and type 'bool' in operation"

llvm-svn: 132674

this. My suggestion assumed a viable erase method for iterators on
SmallPtrSet.

This patch restores his original pattern.

llvm-svn: 132673

Fix PR10053: Improve diagnostics and error recovery for code which some compilers incorrectly accept due to a lack of proper support for two-phase name lookup.

llvm-svn: 132672

llvm-svn: 132671

llvm-svn: 132669

llvm-svn: 132668

Drop most of InitializationSequence::SequenceKind's values. They didn't really contain any information that the step array didn't contain too. This makes debugging dumps a bit less informative, but probably not significantly so. The advantage is that the redundancy is gone, so the code is easier to understand.
ReferenceBinding is still there, because it is used in some unclear code.

llvm-svn: 132667

llvm-svn: 132666