The register allocator needs to adjust its live interval unions when that happens.

llvm-svn: 127774

llvm-svn: 127773

The live range of a virtual register may change which invalidates the cached
interference information.

llvm-svn: 127772

llvm-svn: 127771

rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.

This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.

llvm-svn: 127766

llvm-svn: 127764

plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.

llvm-svn: 127763

llvm-svn: 127761

llvm-svn: 127757

can event.

llvm-svn: 127741

llvm-svn: 127728

report_fatal_error() invokes exit(). We know report_fatal_error() might not write messages to stderr when any errors were detected on FD == 2.

llvm-svn: 127726

FIXME: It is a temporal hack. We should detect as many "special file name" as possible.
llvm-svn: 127724

FIXME: We should use sys::fs::unique_file() in future.
llvm-svn: 127723

llvm-svn: 127721

llvm-svn: 127720

chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.

This fixes <rdar://problem/8613163>.

llvm-svn: 127718

llvm-svn: 127716

llvm-svn: 127715

1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.

llvm-svn: 127707

llvm-svn: 127705

accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.

llvm-svn: 127700

After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.

This is only the analysis part. The information is not used for anything yet.

llvm-svn: 127698

llvm-svn: 127697

llvm-svn: 127694

llvm-svn: 127691

llvm-svn: 127684

llvm-svn: 127683

llvm-svn: 127681

llvm-svn: 127680

llvm-svn: 127678

- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions

llvm-svn: 127677

MCFixupKind.  This is the same technique that is used elsewhere in MC.

llvm-svn: 127676

when building with assertions disabled.

llvm-svn: 127675

llvm-svn: 127674

memory builtins as equivalent to malloc/free.

This is different from any attribute we have. For example, you can delete the
allocators when their result is unused, but you can't collapse two calls to the
same function, even if no global/memory state has changed in between. The
noalias return states that the result does not alias any other pointer, but
instcombine optimizes malloc() as though the result is non-null for the purpose
of eliminating unused pointers.

llvm-svn: 127673

v2 = bitcast v1
...
v3 = bitcast v2
...
   = v3
=>
v2 = bitcast v1
...
   = v1
if v1 and v3 are of in the same register class.

bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.

rdar://9104514

llvm-svn: 127668

of pointers in an std::map.

llvm-svn: 127650

zext(undef) = 0, because the top bits will be zero.

llvm-svn: 127649

in the instruction tables and fixed a few bugs that
were causing decode conflicts.  Rudimentary tests
are coming up in the next patch.

llvm-svn: 127646