llvm-svn: 97488

llvm-svn: 97485

tantalyzing enough that people keep trying to use it.

llvm-svn: 97483

bit should be set to 0 instead of 1.

llvm-svn: 97481

OPC_SwitchOpcode to use a table lookup instead of having to go
through the interpreter for this.

llvm-svn: 97469

an APInt.

llvm-svn: 97467

by Micah Villmow for PR6335.

llvm-svn: 97461

llvm-svn: 97460

llvm-svn: 97459

llvm-svn: 97458

llvm-svn: 97453

llvm-svn: 97450

llvm-svn: 97449

llvm-svn: 97448

llvm-svn: 97446

llvm-svn: 97443

llvm-svn: 97441

ComplexPattern at the root be generated multiple times, once
for each opcode they are part of.  This encourages factoring
because the opcode checks get treated just like everything
else in the matcher.

llvm-svn: 97439

to a scope where every child starts with a CheckOpcode, but
executes more efficiently.  Enhance DAGISelMatcherOpt to 
form it.

This also fixes a bug in CheckOpcode: apparently the SDNodeInfo
objects are not pointer comparable, we have to compare the
enum name.

llvm-svn: 97438

llvm-svn: 97427

llvm-svn: 97426

(which gets #included into the middle of each 
target's DAGISel class) into a .cpp file where it is
only compiled once.

llvm-svn: 97425

case of MorphNodeTo directly.

llvm-svn: 97417

llvm-svn: 97408

APInt.  Be certain to set the integer bit in an x87 extended-precision
significand so that we don't accidentally make a pseudo-NaN.

llvm-svn: 97382

It gets its own implementation totally divorced from the (presumably
performance-sensitive) routines which parse into a uint64_t.

Add APInt::operator|=(uint64_t), which is situationally much better than
using a full APInt.

llvm-svn: 97381

llvm-svn: 97377

llvm-svn: 97376

llvm-svn: 97375

llvm-svn: 97374

llvm-svn: 97372

llvm-svn: 97371

llvm-svn: 97370

llvm-svn: 97366

payloads.  APFloat's internal folding routines always make QNaNs now,
instead of sometimes making QNaNs and sometimes SNaNs depending on the
type.

llvm-svn: 97364

llvm-svn: 97360

after LSR, so that clients can opt in.

llvm-svn: 97357

Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354

defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

llvm-svn: 97348