llvm-svn: 132824

llvm-svn: 132822

llvm-svn: 132821

With this I am able to bootstrap clang with early tail duplication enabled
for any small bb and setting tail-dup-size to a relatively large value(8) to
stress this code.

llvm-svn: 132816

Chris fixed this README a while back by changing how clang generates code for structs like the given struct.

llvm-svn: 132815

llvm-svn: 132814

causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811

Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine.  Part of rdar://9562809.

The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now.

llvm-svn: 132809

eh edges. Swap the order of the checks to avoid it.

llvm-svn: 132806

llvm-svn: 132805

llvm-svn: 132803

VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802

llvm-svn: 132800

pad, separating the exception and selector calls from the new lpad.  Teaching
it not to do that, or to properly adjust the CFG afterwards, is out of
scope because it would require the other edges to the landing pad to be split
as well (effectively).  Instead, just recover from the most likely cases
during inlining.  The best long-term solution is to change the exception
representation and commit to either requiring or not requiring the more
complex edge-splitting logic;  this is just a shorter-term hack.

llvm-svn: 132799

No functionality change.

llvm-svn: 132798

llvm-svn: 132797

llvm-svn: 132795

llvm-svn: 132790

Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.

llvm-svn: 132789

I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

llvm-svn: 132788

Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change.

llvm-svn: 132785

Radar 9558930.

llvm-svn: 132782

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781

llvm-svn: 132777

llvm-svn: 132776

llvm-svn: 132775

Patch by Pekka Jaaskelainen. 

llvm-svn: 132774

llvm-svn: 132772

llvm-svn: 132771

Patch by Jake Waskett!

llvm-svn: 132770

llvm-svn: 132768

llvm-svn: 132767

assuming that all offsets are legal vector accesses, and thus trying to access
the float member of { <2 x float>, float } as the 3rd element of the first
member.

llvm-svn: 132766

of the frame then increase the maximum alignment of the frame to
match.

Fixes PR6965

llvm-svn: 132764

No functional change.

Part of PR6965

llvm-svn: 132763

former was using the size of the entire alloca, whereas the latter was correctly using
the allocated size of the immediate type being converted (which may differ from the size
of the alloca). This fixes PR10082.

llvm-svn: 132759

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132756

llvm-svn: 132751

llvm-svn: 132749