This was exposed as a result of something else that was recently fixed.

llvm-svn: 69004

expression or statement serialization before we can test them.

llvm-svn: 69002

llvm-svn: 68998

llvm-svn: 68997

promoted to legal types without changing the type of the vector.  This is
following a suggestion from Duncan
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/019923.html).
The transformation that used to be done during type legalization is now
postponed to DAG legalization.  This allows the BUILD_VECTORs to be optimized
and potentially handled specially by target-specific code.

It turns out that this is also consistent with an optimization done by the
DAG combiner: a BUILD_VECTOR and INSERT_VECTOR_ELT may be combined by
replacing one of the BUILD_VECTOR operands with the newly inserted element;
but INSERT_VECTOR_ELT allows its scalar operand to be larger than the
element type, with any extra high bits being implicitly truncated.  The
result is a BUILD_VECTOR where one of the operands has a type larger the
the vector element type.

Any code that operates on BUILD_VECTORs may now need to be aware of the
potential type discrepancy between the vector element type and the
BUILD_VECTOR operands.  This patch updates all of the places that I could
find to handle that case.

llvm-svn: 68996

implies an all-zero bit pattern.

llvm-svn: 68994

llvm-svn: 68992

Northover.

llvm-svn: 68991

llvm-svn: 68990

llvm-svn: 68989

handle the definition of __builtin_va_list on x86-64, eliminate the
forced -triple in PCH tests to get better coverage.

llvm-svn: 68988

 - No functionality change.

llvm-svn: 68987

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

llvm-svn: 68985

Objective-C types and record types for the moment.

llvm-svn: 68984

codegenerator bug.

llvm-svn: 68983

llvm-svn: 68982

llvm-svn: 68981

llvm-svn: 68980

llvm-svn: 68979

llvm-svn: 68978

llvm-svn: 68977

setter/getter synthesis.

llvm-svn: 68976

Fixed crasher in <rdar://problem/6780904> [irgen] Assertion failed: (Result == conversionOK && "UTF-8 to UTF-16 conversion failed"), function GetAddrOfConstantCFString, file CodeGenModule.cpp, line 1063.

Still a diagnostic related FIXME (will discuss with Daniel/Fariborz offline).

llvm-svn: 68975

llvm-svn: 68974

Right now, Debugging information to encode scopes (DW_TAG_lexical_block) relies on DBG_LABEL. Unfortunately this intefers with the quality of optimized code. 
This patch updates dwarf writer to encode scoping information in DWARF only in FastISel mode.

llvm-svn: 68973

llvm-svn: 68972

llvm-svn: 68971

llvm-svn: 68969

Change diagnostic as a result of researching <rdar://problem/6779809> missing interface name in "error: cannot declare variable inside a class, protocol or category ''.

Since ObjC 2.0 class "extensions" have a null name, the diagnostic above is actually "correct". Nevertheless, it is confusing. Decided to remove the name entirely (from my perspective, it didn't add any value). Also simplified the text of the diagnostic a bit.

llvm-svn: 68967

 - Ted, please check.

 - Missing test case because PTH won't reliably cache the tokens in a
   test case. *cough*

llvm-svn: 68966

the unlikely event that the filename IDs in the stored line table end
up being different from the filename IDs in the newly-created line
table.

llvm-svn: 68965

Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.

llvm-svn: 68964

properly cope with #line directives in PCH files.

llvm-svn: 68963

 - Add patterns for h-register extract, which avoids a shift and mask,
   and in some cases a temporary register.
 - Add address-mode matching for turning (X>>(8-n))&(255<<n), where
   n is a valid address-mode scale value, into an h-register extract
   and a scaled-offset address.
 - Replace X86's MOV32to32_ and related instructions with the new
   target-independent COPY_TO_SUBREG instruction.

On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.

These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.

llvm-svn: 68962

This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.

llvm-svn: 68961

Factor the internals of SourceManager (specially, LineTableInfo) into a separate Internals header. No functionality change

llvm-svn: 68960

ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.

llvm-svn: 68959

llvm-svn: 68958

in multiple classes in the case that the classes are all
in subset/superset relations. This function is used by the
fast-isel emitter, which always wants the super-most set.

llvm-svn: 68957