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  1. Feb 20, 2011
  2. Feb 18, 2011
  3. Feb 17, 2011
  4. Feb 15, 2011
  5. Feb 14, 2011
  6. Feb 13, 2011
  7. Feb 12, 2011
    • Jim Grosbach's avatar
      AsmMatcher custom operand parser failure enhancements. · 861e49ce
      Jim Grosbach authored
      Teach the AsmMatcher handling to distinguish between an error custom-parsing
      an operand and a failure to match. The former should propogate the error
      upwards, while the latter should continue attempting to parse with
      alternative matchers.
      
      Update the ARM asm parser accordingly.
      
      llvm-svn: 125426
      861e49ce
  8. Feb 11, 2011
  9. Feb 10, 2011
  10. Feb 07, 2011
    • Bruno Cardoso Lopes's avatar
      Implement support for custom target specific asm parsing of operands. · 2315beba
      Bruno Cardoso Lopes authored
      Motivation: Improve the parsing of not usual (different from registers or
      immediates) operand forms.
      
      This commit implements only the generic support. The ARM specific modifications
      will come next.
      
      A table like the one below is autogenerated for every instruction
      containing a 'ParserMethod' in its AsmOperandClass
      
      static const OperandMatchEntry OperandMatchTable[20] = {
       /* Mnemonic, Operand List Mask, Operand Class, Features */
       { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 },
       { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM },
      
      A matcher function very similar (but lot more naive) to
      MatchInstructionImpl scans the table. After the mnemonic match, the
      features are checked and if the "to be parsed" operand index is
      present in the mask, there's a real match. Then, a switch like the one
      below dispatch the parsing to the custom method provided in
      'ParseMethod':
      
       case MCK_Coproc:
         return TryParseCoprocessorOperandName(Operands);
      
      llvm-svn: 125030
      2315beba
  11. Feb 05, 2011
  12. Feb 04, 2011
    • Jason W Kim's avatar
      · d2e2f56c
      Jason W Kim authored
      Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
      (yes, this is different from R_ARM_CALL)
      
      - Adds a new method getARMBranchTargetOpValue() which handles the
        necessary distinction between the conditional and unconditional br/bl
        needed for ARM/ELF
      
      At least for ARM mode, the needed fixup for conditional versus unconditional
      br/bl is identical, but the ARM docs and existing ARM tools expect this
      reloc type...
      
      Added a few FIXME's for future naming fixups in ARMInstrInfo.td
      
      llvm-svn: 124895
      d2e2f56c
    • Daniel Dunbar's avatar
      MC/AsmParser: Add support for allowing the conversion process to fail (via · 66193404
      Daniel Dunbar authored
      custom conversion functions).
      
      llvm-svn: 124872
      66193404
    • Daniel Dunbar's avatar
      MC/AsmMatcher: Add support for custom conversion functions. · 77b7c3f1
      Daniel Dunbar authored
      llvm-svn: 124870
      77b7c3f1
    • David Greene's avatar
      · 094442d3
      David Greene authored
      Silence uninitialized value warnings.
      
      llvm-svn: 124869
      094442d3
    • Jim Grosbach's avatar
      Tidy up a bit. · cd25b86f
      Jim Grosbach authored
      llvm-svn: 124832
      cd25b86f
  13. Feb 03, 2011
  14. Feb 02, 2011
    • Kevin Enderby's avatar
      Changed the TableGen created MatchInstructionImpl() setting of ErrorInfo. · 96f6e379
      Kevin Enderby authored
      The algorithm for identifying which operand is invalid will now always point to
      some operand and not the mnemonic sometimes.  The change is now that ErrorInfo
      is the index of the highest operand that does not match for any of the matching
      mnemonics records.  And no longer the ~0U value when the mnemonic matches and
      not every record with a matching mnemonic has the same mismatching operand
      index.
      
      llvm-svn: 124734
      96f6e379
  15. Feb 01, 2011
    • David Greene's avatar
      · 433c6180
      David Greene authored
      [AVX] Implement EnforceSmallerThan for mixed int/fp type lists.  This
      makes type checking for extract_subvector and insert_subvector more
      robust and will allow stricter typechecking of more patterns in the
      future.
      
      This change handles int and fp as disjoint sets so that it will
      enforce integer types to be smaller than the largest integer type and
      fp types to be smaller than the largest fp type.  There is no attempt
      to check type sizes across the int/fp sets.
      
      llvm-svn: 124672
      433c6180
  16. Jan 28, 2011
  17. Jan 27, 2011
  18. Jan 26, 2011
  19. Jan 25, 2011
  20. Jan 24, 2011
    • David Greene's avatar
      · 127fd1d5
      David Greene authored
      [AVX] Add type checking support for vector/subvector type constraints.
      This will be used to check patterns referencing a forthcoming
      INSERT_SUBVECTOR SDNode.  INSERT_SUBVECTOR in turn is very useful for
      matching to VINSERTF128 instructions and complements the already
      existing EXTRACT_SUBVECTOR SDNode.
      
      llvm-svn: 124145
      127fd1d5
  21. Jan 22, 2011
  22. Jan 21, 2011
  23. Jan 20, 2011
  24. Jan 19, 2011
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