relocation sections.

llvm-svn: 73038

llvm-svn: 73025

converting from an MMX vector to an i64.

llvm-svn: 73024

llvm-svn: 73017

Also create isValidElementType for ArrayType, PointerType, StructType and
VectorType.

Make LLParser use them. This closes up some holes like an assertion failure on:

  %x = type {label}

but largely doesn't change any semantics. The only thing we accept now which
we didn't before is vectors of opaque type such as "<4 x opaque>". The opaque
can be resolved to an int or float when linking.

llvm-svn: 73016

Nice addition to the examples and also a starting point for Sanjiv to work on.

llvm-svn: 73013

on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.

llvm-svn: 73012

crash LLVM first.

llvm-svn: 73011

llvm-svn: 73010

instructions.

llvm-svn: 73009

to gcc.

llvm-svn: 73008

Fixes PR4314.

llvm-svn: 73007

sometimes it can find simplifications that won't be found otherwise.

llvm-svn: 73006

llvm-svn: 73003

Instructions.

llvm-svn: 73002

SCEVCouldNotCompute, and not SCEVUnknown.

llvm-svn: 72999

types.

llvm-svn: 72993

llvm-svn: 72992

llvm-svn: 72991

llvm-svn: 72990

Also, there were a bunch of flags with no text in --help because the square
brackets were in the wrong place. I've fixed those too.

llvm-svn: 72989

nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.

llvm-svn: 72988

llvm-svn: 72987

llvm-svn: 72986

llvm-svn: 72985

conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.

llvm-svn: 72983

llvm-svn: 72982

integer type to be consistent with normal operation legalization.  No visible
change because nothing is actually using this at the moment.

llvm-svn: 72980

llvm-svn: 72975

llvm-svn: 72970

llvm-svn: 72969

llvm-svn: 72965

Update code generator to use this attribute and remove NoImplicitFloat target option.
Update llc to set this attribute when -no-implicit-float command line option is used.

llvm-svn: 72959

build vectors with i64 elements will only appear on 32b x86 before legalize.
Since vector widening occurs during legalize, and produces i64 build_vector 
elements, the dag combiner is never run on these before legalize splits them
into 32b elements.

Teach the build_vector dag combine in x86 back end to recognize consecutive 
loads producing the low part of the vector.

Convert the two uses of TLI's consecutive load recognizer to pass LoadSDNodes
since that was required implicitly.

Add a testcase for the transform.

Old:
	subl	$28, %esp
	movl	32(%esp), %eax
	movl	4(%eax), %ecx
	movl	%ecx, 4(%esp)
	movl	(%eax), %eax
	movl	%eax, (%esp)
	movaps	(%esp), %xmm0
	pmovzxwd	%xmm0, %xmm0
	movl	36(%esp), %eax
	movaps	%xmm0, (%eax)
	addl	$28, %esp
	ret

New:
	movl	4(%esp), %eax
	pmovzxwd	(%eax), %xmm0
	movl	8(%esp), %eax
	movaps	%xmm0, (%eax)
	ret

llvm-svn: 72957

Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.

llvm-svn: 72955

llvm-svn: 72954

llvm-svn: 72953

llvm-svn: 72952

llvm-svn: 72950

llvm-svn: 72949