llvm-svn: 105862

that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377

llvm-svn: 104254

llvm-svn: 104175

llvm-svn: 103806

while debugging what's mishandled about them in the post-RA pass.

llvm-svn: 103805

changes before doing phi lowering for switches.

llvm-svn: 102809

just remove them all.  Radar 7873207 (working around the root problem of
Radar 7759363).

llvm-svn: 101604

llvm-svn: 101043

llvm-svn: 97765

llvm-svn: 92594

llvm-svn: 90970

The MO reference to a MachineOperand can be invalidated by
MachineInstr::addOperand. Don't even use it for debugging.

llvm-svn: 90381

Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.

llvm-svn: 89471

llvm-svn: 88682

llvm-svn: 87015

llvm-svn: 86634

Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 

llvm-svn: 86628

Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.

llvm-svn: 86098

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

 - Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682

llvm-svn: 85412

Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.

llvm-svn: 85166

llvm-svn: 85146

Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.

llvm-svn: 85145

llvm-svn: 85127

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84727

Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.

llvm-svn: 84691

llvm-svn: 84658

llvm-svn: 84273

llvm-svn: 84248

llvm-svn: 84011

llvm-svn: 83695

is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687

MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.

llvm-svn: 83249

llvm-svn: 83223

Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.

llvm-svn: 83218