Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 

When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.

This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.

Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.

llvm-svn: 77582

a Twine, e.g., for names).
 - I am a little ambivalent about this; we don't want the string conversion of
   utostr, but using overload '+' mixed with string and integer arguments is
   sketchy. On the other hand, this particular usage is something of an idiom.

llvm-svn: 77579

declaration for them.

llvm-svn: 77578

explicitly.

llvm-svn: 77576

llvm-svn: 77570

llvm-svn: 77568

due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565

llvm-svn: 77559

llvm-svn: 77558

llvm-svn: 77557

llvm-svn: 77553

llvm-svn: 77549

llvm-svn: 77522

llvm-svn: 77521

there is no new block added to the free list. Therefore on the next
startFunctionBody call, a new slab must be allocated.

llvm-svn: 77520

llvm-svn: 77519

llvm-svn: 77517

llvm-svn: 77516

llvm-svn: 77513

 - Call RAUW to delete all instructions (this is a patch from Nick Lewycky).

llvm-svn: 77512

llvm-svn: 77511

now that TargetOperandInfo does the heavy lifting.

llvm-svn: 77508

llvm-svn: 77507

llvm-svn: 77505

   and convert code to using it, instead of having lots of things
   poke the isLookupPtrRegClass() method directly.

2. Make PointerLikeRegClass contain a 'kind' int, and store it in
   the existing regclass field of TargetOperandInfo when the
   isLookupPtrRegClass() predicate is set.  Make getRegClass pass
   this into TargetRegisterInfo::getPointerRegClass(), allowing
   targets to have multiple ptr_rc things.

llvm-svn: 77504

support multiple different pointer register classes.

llvm-svn: 77501

- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500

llvm-svn: 77495

llvm-svn: 77494

llvm-svn: 77482

llvm-svn: 77480

llvm-svn: 77477

llvm-svn: 77476

wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468

overloaded types for intrinsic parameters.

llvm-svn: 77466

Re-apply previous changes and improve column padding performance some more.

llvm-svn: 77461

llvm-svn: 77459

 - Provides static constructors for doing number to string conversions without
   using temporaries.

 - There are several ways to do this, I think given the Twine constraints this
   is the simplest one.

 - One FIXME for fast number -> hex conversion.

 - Added another comment on one last major bit of perf work Twines need, which
   is to make raw_svector_ostream more efficient.

llvm-svn: 77445

llvm-svn: 77444

llvm-svn: 77442