This resolves the last of the PR14606 failures in the GDB 7.5 test
suite by implementing an optional name field for
DW_TAG_imported_modules/DIImportedEntities and using that to implement
C++ namespace aliases (eg: "namespace X = Y;").

llvm-svn: 182328

Replacing an assertion with an error - at least we won’t crash

llvm-svn: 182326

llvm-svn: 182325

llvm-svn: 182324

This changes the setting target.load-script-from-symbol-file to be a ternary enum value:
default (the default value) will NOT load the script files but will issue a warning suggesting workarounds
yes will load the script files
no will not load the script files AND will NOT issue any warning

if you change the setting value from default to yes, that will then cause the script files to be loaded
(the assumption is you didn't know about the setting, got a warning, and quickly want to remedy it)

if you have a settings set command for this in your lldbinit file, be sure to change "true" or "false" into an appropriate "yes" or "no" value

llvm-svn: 182323

The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes.

llvm-svn: 182321

AsmPrinter::EmitLinkage() does not handle dllimport linkage.  The LLVM
verifier should also be fixed to reject this.

llvm-svn: 182320

llvm-svn: 182317

protocols that declare the same property of incompatible
types, issue a warning when class implementation synthesizes 
the property. // rdar://13075400

llvm-svn: 182316

llvm-svn: 182315

As discussed, LoopUtils.h is a better name.

llvm-svn: 182314

llvm-svn: 182310

llvm-svn: 182309

llvm-svn: 182308

llvm-svn: 182307

By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306

llvm-svn: 182305

GetPageSize wraps sysconf(_SC_PAGESIZE) on POSIX platforms, but
sysconf resides in libc.  To make this libc-independent on Linux,
move the wrapper to sanitizer_mac.cc and return the Linux-specific
constant EXEC_PAGESIZE in the sanitizer_linux.cc implementation.

llvm-svn: 182303

llvm-svn: 182302

llvm-svn: 182301

Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.

No functionality change intended.

llvm-svn: 182300

Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

llvm-svn: 182299

[NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter.  This was causing a symbol name error in the output PTX.

llvm-svn: 182298

llvm-svn: 182297

As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

llvm-svn: 182296

When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

llvm-svn: 182295

llvm-svn: 182294

R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293

llvm-svn: 182292

The -debug-only option is only available on asserts builds.

llvm-svn: 182291

llvm-svn: 182290

This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286

The hardware supports rotr and not rotl.

llvm-svn: 182285

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284

This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282

VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

llvm-svn: 182281

llvm-svn: 182280