separately-allocated DefinitionData structure. Introduce various
functions that will help with the separation of declarations from
definitions (isThisDeclarationADefinition(), hasDefinition(),
getDefinition()).

llvm-svn: 147408

llvm-svn: 147407

getCanonicalDecl() when putting ObjCProtocolDecls into a set. This is
groundwork for making ObjCProtocolDecl redeclarable.

llvm-svn: 147406

take precedence over command line options. Fixes PR10113.

llvm-svn: 147405

llvm-svn: 147404

PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers.

llvm-svn: 147403

llvm-svn: 147402

llvm-svn: 147401

llvm-svn: 147400

The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147399

llvm-svn: 147395

llvm-svn: 147394

llvm-svn: 147393

Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected.

llvm-svn: 147392

'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.

llvm-svn: 147391

See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.

This makes the source of the bug more obvious
than the other asserts triggering later on did.

llvm-svn: 147390

llvm-svn: 147388

features needed for a particular module to be available. This allows
mixed-language modules, where certain headers only work under some
language variants (e.g., in C++, std.tuple might only be available in
C++11 mode).

llvm-svn: 147387

Mingw32 target has not supported integrated-as yet.

llvm-svn: 147386

llvm-svn: 147385

Also temporarily remove the assumption from IR gen that we can emit IR for every
constant we can fold, since it isn't currently true in C++11, to fix PR11676.

Original comment from r147271:

constexpr: perform zero-initialization prior to / instead of performing a
constructor call when appropriate. Thanks to Eli for spotting this.

llvm-svn: 147384

llvm-svn: 147383

Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

llvm-svn: 147382

llvm-svn: 147379

python bindinds.
patch by Tom Schuster!

llvm-svn: 147378

llvm-svn: 147373

llvm-svn: 147372

llvm-svn: 147371

Add FMA4 feature flag. Intrinsics coming soon. Also make sse4a feature flag imply sse3. Matches gcc behavior.

llvm-svn: 147370

Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.

llvm-svn: 147369

llvm-svn: 147368

llvm-svn: 147367

Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.

llvm-svn: 147366

llvm-svn: 147365

llvm-svn: 147364

llvm-svn: 147363

llvm-svn: 147362

Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.

llvm-svn: 147361

Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.

llvm-svn: 147360

1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

llvm-svn: 147359