While making lld build under the tools directory I decided to refactor how this
works.

There is now a macro, add_llvm_external_project, which takes the name of the
expected subdirectory. This sets up two CMake options.

 * LLVM_EXTERNAL_${NAME}_SOURCE_DIR
     This is the path to the source. It defaults to
     ${CMAKE_CURRENT_SOURCE_DIR}/${name}.
 * LLVM_EXTERNAL_${NAME}_BUILD
     Enable and disable building the tool as part of LLVM.

I chose LLVM_EXTERNAL_${NAME} as a prefix so they all show up together in the
GUI.

llvm-svn: 155654

'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails.

llvm-svn: 155653

Fixed SmallMap test. The order of items is undefined in DenseMap. So being checking the increment for big mode, we can only check that all items are in map.

llvm-svn: 155651

On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.

llvm-svn: 155630

llvm-svn: 155626

Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.

llvm-svn: 155618

elements to minimize the number of multiplies required to compute the
final result. This uses a heuristic to attempt to form near-optimal
binary exponentiation-style multiply chains. While there are some cases
it misses, it seems to at least a decent job on a very diverse range of
inputs.

Initial benchmarks show no interesting regressions, and an 8%
improvement on SPASS. Let me know if any other interesting results (in
either direction) crop up!

Credit to Richard Smith for the core algorithm, and helping code the
patch itself.

llvm-svn: 155616

llvm-svn: 155604

the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.

rdar://11318438

llvm-svn: 155601

llvm-svn: 155599

llvm-svn: 155589

a failure if run on an Intel Atom with post RA instruction scheduling.

llvm-svn: 155587

Comparing ~0UL with an unsigned will always return false when long is 64 bits long.

llvm-svn: 155568

llvm-svn: 155567

llvm-svn: 155566

Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.

llvm-svn: 155565

This reverts commit 76271a3366731d4c372fdebcd8d3437e6e09a61b.

as it's breaking the bots.

llvm-svn: 155562

- FlatArrayMap. Very simple map container that uses flat array inside.
- MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount.
- SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode. 

Also added unittests for new classes and update for ProgrammersManual.
For more details about new classes see ProgrammersManual and comments in sourcecode.

llvm-svn: 155557

This function is only used for a heuristic during -join-physregs. It
doesn't need floating point.

llvm-svn: 155554

llvm-svn: 155553

Cross-class joins have been normal and fully supported for a while now.
With TableGen generating the getMatchingSuperRegClass() hook, they are
unlikely to cause problems again.

llvm-svn: 155552

Remove the heuristic for disabling cross-class joins. The greedy
register allocator can handle the narrow register classes, and when it
splits a live range, it can pick a larger register class.

Benchmarks were unaffected by this change.

<rdar://problem/11302212>

llvm-svn: 155551

Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.

llvm-svn: 155538

Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.

llvm-svn: 155537

llvm-svn: 155536

llvm-svn: 155532

in poor taste.

Talking through some alternate solutions with Chandler.

llvm-svn: 155530

llvm-svn: 155522

llvm-svn: 155519

of a precise count. Also, move RRInfo's Partial field into PtrState,
now that it won't increase the size.

llvm-svn: 155513

These lists exclude invoke unwind edges and loop backedges which
are being ignored. This makes it easier to ignore them
consistently.

llvm-svn: 155500

When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

llvm-svn: 155499

llvm-svn: 155486

Fix 12592. Patch by Matt Pharr.

llvm-svn: 155480

llvm-svn: 155477

llvm-svn: 155475

MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144

llvm-svn: 155470

<rdar://problem/11291436>.

llvm-svn: 155468

constants in C++11 mode. I have no idea why it required such particular
circumstances to get here, the code seems clearly to rely upon unchecked
assumptions.

Specifically, when we decide to form an index into a struct type, we may
have gone through (at least one) zero-length array indexing round, which
would have left the offset un-adjusted, and thus not necessarily valid
for use when indexing the struct type.

This is just an canonicalization step, so the correct thing is to refuse
to canonicalize nonsensical GEPs of this form. Implemented, and test
case added.

Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit
him with most of the debugging, and preventing me from writing the wrong
code.

llvm-svn: 155466

r154362 was supposed to delete this bit, but obviously didn't.

rdar://11305594

llvm-svn: 155465