is morphed by AnalyzeNewNode into a previously
processed node, and different result values of
that node are remapped to values with different
nodes, then we could end up using wrong values
here [we were assuming that all results remap
to values with the same underlying node].  This
seems theoretically possible, but I don't have
a testcase.  The meat of the patch is in the
changes to AnalyzeNewNode/AnalyzeNewValue and
ReplaceNodeWith.  While there, I changed names
like RemapNode to RemapValue, since it really
remaps values.  To tell the truth, I would be
much happier if we were only remapping nodes
(it would simplify a bunch of logic, and allow
for some cute speedups) but I haven't yet worked
out how to do that.

llvm-svn: 58372

llvm-svn: 58371

llvm-svn: 58370

- Create and update spill slot live intervals.
- Lots of bug fixes.

llvm-svn: 58367

EnableFastISelAbort variables for Release mode instead of
using ifdefs in the code.

llvm-svn: 58350

llvm-svn: 58340

ppcf128 to i32 conversion and expand it into a code
sequence like in LegalizeDAG.  This needs custom
ppc lowering of FP_ROUND_INREG, so turn that on and
make it work with LegalizeTypes.  Probably PPC should
simply custom lower the original conversion.

llvm-svn: 58329

id could end up being wrong mostly because of
forgetting to remap new nodes that morphed into
processed nodes through CSE.

llvm-svn: 58323

llvm-svn: 58320

llvm-svn: 58319

llvm-svn: 58314

llvm-svn: 58312

Avoid putting a split past the end of the live range; always shrink wrap live interval in the barrier mbb.

llvm-svn: 58309

llvm-svn: 58297

llvm-svn: 58294

llvm-svn: 58290

Add setSubgraphColor to color an entire portion of a SelectionDAG.  This
will be used to support debug features in TableGen.

llvm-svn: 58257

Fix PR2634.  Create new virtual registers from spills early so that we
can give it the same stack slot as the spilled interval if it is folded.
This prevents the fold/unfold code from pointing to the wrong register.

llvm-svn: 58255

(and a bunch of other node types).  While there, I
added a doNotCSE predicate and used it to reduce code
duplication (some of the duplicated code was wrong...).
This fixes ARM/cse-libcalls.ll when using LegalizeTypes. 

llvm-svn: 58249

worklist twice: UpdateNodeOperands could morph
a new node into a node already on the worklist.
We would then recalculate the NodeId for this
existing node and add it to the worklist.  The
testcase is ARM/cse-libcalls.ll, the problem
showing up once UpdateNodeOperands is taught to
do CSE for calls.

llvm-svn: 58246

codegen infrastructure, by default.  Please report
any breakage to the mailing lists.

llvm-svn: 58232

For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them.

llvm-svn: 58230

150, based on llvm-test measurements.

llvm-svn: 58225

Do not shrink wrap live interval in a mbb if it's livein any of its successor blocks. The mbb can be revisited again after all of the successors are processed.

llvm-svn: 58184

llvm-svn: 58174

to reflect that.

llvm-svn: 58145

target-independent code to target-specific code. This prevents it
from running on targets that aren't using fast-isel.

In addition to saving compile time, this addresses the problem
that not all targets are prepared for it. In order to use this
pass, all instructions must declare all their fixed uses and
defs of physical registers.

llvm-svn: 58144

If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot.

llvm-svn: 58129

llvm-svn: 58102

llvm-svn: 58072

llvm-svn: 58068

llvm-svn: 58057

Committing a good chunk of the pre-register allocation live interval splitting pass. It's handling simple cases and appear to do good things. Next: avoid splitting an interval multiple times; renumber registers when possible; record stack slot live intervals for coloring; rematerialize defs when possible.

llvm-svn: 58044

with the result number.

llvm-svn: 58041

llvm-svn: 57973

may return i8, which can result in SELECT nodes for
which the type of the condition is i8, but there are
no patterns for select with i8 condition.  Tweak the
LegalizeTypes logic to avoid this as much as possible.
This isn't a real fix because it is still perfectly
possible to end up with such select nodes - CellSPU
needs to be fixed IMHO.

llvm-svn: 57968

ADDC/ADDE/SUBC/SUBE if the target supports it.

llvm-svn: 57967

that is not of type MVT::i1 in SELECT and SETCC nodes.
Relax the LegalizeTypes SELECT condition promotion
sanity checks to allow other condition types than i1.

llvm-svn: 57966

to have a different type to the vector element
type.  This should be fairly harmless because in
the past guys like this were being built all over
the place (and were cleaned up when I added this
check).  The reason for relaxing this check is
that it helps LegalizeTypes legalize vector
shuffles: the mask is a BUILD_VECTOR that it is
*not always possible* to legalize while keeping it
a BUILD_VECTOR (vector_shuffle requires the mask
to be a BUILD_VECTOR, as opposed to a vector with
the right vector type).  With this check it is even
harder to legalize the mask - turning the check off
means that LegalizeTypes manages to legalize almost
all vector shuffles encountered in practice.  The
correct solution is to change vector_shuffle to be a
variadic node with the mask built into it as operands.
While waiting for that change, this hack stops the
problem with vector_shuffle from blocking the turning
on of LegalizeTypes.

llvm-svn: 57965

llvm-svn: 57946