vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144

encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.

llvm-svn: 118143

set breakpoints at the different locations where
an exception could be thrown, so that exceptions
thrown by expressions are properly caught.

llvm-svn: 118142

llvm-svn: 118141

printOperand() asm printer helper functions. rdar://8425198

llvm-svn: 118140

llvm-svn: 118139

parameter name.

Fixes PR8012.

llvm-svn: 118138

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427

llvm-svn: 118135

latencies) of loads.

llvm-svn: 118134

llvm-svn: 118133

ensuring that they cover all of their child nodes. There's still a
clang_getCursor()-related issue with CXXFunctionalCastExprs with
CXXConstructExprs as children (see FIXME in the test case); I'll look
at that separately.

llvm-svn: 118132

llvm-svn: 118131

llvm-svn: 118130

llvm-svn: 118129

llvm-svn: 118128

llvm-svn: 118127

llvm-svn: 118126

instructions as isCodeGenOnly in the parent class instead of
sprinkling it throughout the .td files.

llvm-svn: 118125

llvm-svn: 118124

for a global variable that we had replaced with
a reference to a slot in the input array.

llvm-svn: 118123

llvm-svn: 118122

llvm-svn: 118121

llvm-svn: 118120

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

clang are using.

llvm-svn: 118118

threshold given to createFunctionInliningPass().

Both opt -O3 and clang would silently ignore the -inline-threshold option.

llvm-svn: 118117

on i386 platforms, leading to crashes on simple
expressions.

llvm-svn: 118114

limits on their own.

llvm-svn: 118113

that have complicated tying going on.

llvm-svn: 118112

llvm-svn: 118111

llvm-svn: 118110

within an @implementation, but we have no way to record that information in the AST.
This may cause CursorVisitor to miss these Decls when doing a AST walk.

Fixes <rdar://problem/8595462>.

llvm-svn: 118109

llvm-svn: 118108

llvm-svn: 118107

llvm-svn: 118106

llvm-svn: 118105

filling them in one at a time.  Previously this iterated over the
asmoperands, which left the problem of "holes".  The new approach
simplifies things.

llvm-svn: 118104

llvm-svn: 118103

llvm-svn: 118102