Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

llvm-svn: 139588

llvm-svn: 139583

llvm-svn: 139579

llvm-svn: 139578

llvm-svn: 139577

llvm-svn: 139576

llvm-svn: 139574

which is only relevant with canonical IVs

llvm-svn: 139556

llvm-svn: 139554

destination types are equal!

llvm-svn: 139553

Otherwise this case is now covered by no-iv-rewrite.ll.

llvm-svn: 139552

Fix a failing ELF Thumb test.  I _think_ this is right, but it's not totally clear to me what this test is doing.  Could someone on an ELF platform check?

llvm-svn: 139549

llvm-svn: 139542

llvm-svn: 139541

llvm-svn: 139537

which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.

llvm-svn: 139535

However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528

Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

llvm-svn: 139522

llvm-svn: 139518

llvm-svn: 139517

llvm-svn: 139505

llvm-svn: 139504

This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495

Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

llvm-svn: 139486

llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

llvm-svn: 139459

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

Generate code for Mips32r1 unless a Mips32r2 feature is tested.

llvm-svn: 139433

llvm-svn: 139432

llvm-svn: 139422

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type.  Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs.  Fixes PR10897.

llvm-svn: 139407

llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400

llvm-svn: 139399

llvm-svn: 139397

llvm-svn: 139396

llvm-svn: 139395