llvm-svn: 158446

llvm-svn: 158437

llvm-svn: 158436

llvm-svn: 158434

llvm-svn: 158433

as a scratch register when they are expanded to long branches.

llvm-svn: 158432

to load an immediate that does not fit into 16-bit. 

llvm-svn: 158431

to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size. 

llvm-svn: 158430

compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.

llvm-svn: 158429

Long-branches need access to the global base register to get the destination
address.

llvm-svn: 158428

object for the global base register.

This is the first of a series of patches which implements long branch expansion
for MIPS.

llvm-svn: 158427

delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.

This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.

llvm-svn: 158426

pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419

llvm-svn: 158414

llvm-svn: 158413

llvm-svn: 158410

Patch by Reed Kotler.

llvm-svn: 158382

until this directive is pushed in gas to open source fsf

Patch by Reed Kotler.

llvm-svn: 158381

non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions

Patch by Reed Kotler.

llvm-svn: 158378

llvm-svn: 158250

inserted after the shift-left-logical node.

llvm-svn: 157937

This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929

llvm-svn: 157885

llvm-svn: 157872

llvm-svn: 157867

llvm-svn: 157866

llvm-svn: 157865

custom-lower unaligned load and store nodes.

llvm-svn: 157864

llvm-svn: 157863

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862

the MachineOperand type has a valid offset. 

llvm-svn: 157861

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837

CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730

Patch by Jack Carter.

llvm-svn: 157709

It is better to address sub-registers directly by name instead of
relying on their position in the sub-register list.

llvm-svn: 157703

Benjamin Kramer.

llvm-svn: 157504

llvm-svn: 157496

Delete MipsExpandPseudo.

llvm-svn: 157495

llvm-svn: 157494

llvm-svn: 157493