Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions.

llvm-svn: 40521

llvm-svn: 40123

llvm-svn: 39817

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816

llvm-svn: 39732

llvm-svn: 37651

llvm-svn: 37289

for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285

llvm-svn: 35529

llvm-svn: 35522

llvm-svn: 34984

llvm-svn: 34496

do some common stuff, then on our own add an object file writer (by calling
a concrete function), and then do some finishing stuff, if need be.

llvm-svn: 34032

llvm-svn: 32321

llvm-svn: 31777

empty ranges.

2. Reorg how MachineDebugInfo maintains changes to debug labels.

3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.

4. Revert the merging of compile units until I can get the bugs ironed out.

llvm-svn: 31507

llvm-svn: 31155

it just deletes empty MBB's.  Soon it will do more :)

llvm-svn: 30941

Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095

llvm-svn: 30082