simplified before we do this xform so that our cost model is accurate.

llvm-svn: 31864

llvm-svn: 31861

llvm-svn: 31860

Documentation preview of the upcoming icmp and fcmp instructions that
will replace the various setcc instructions.

llvm-svn: 31859

llvm-svn: 31858

llvm-svn: 31857

This speeds up yacr2 by 7% on a core2.

llvm-svn: 31856

  if (cond) goto BB2
BB1:
    ...
    return;
BB2:
   ...

Move BB1 to the end of the function so that the code falls through in the
non-return case.  This has the effect of moving assert (and other no-return
call) bodies and return blocks out of loops.

llvm-svn: 31855

only do these transformations if there are a small number of phi's.
This speeds up Ptrdist/ks from 2.35s to 2.19s on my mac pro.

llvm-svn: 31853

llvm-svn: 31852

llvm-svn: 31851

the correct options, places the patch content in order that makes sense for
review, and filters cruft out of the patch (like diffs in *.cvs files). It
produces both a NAME.patch.raw (unfiltered) and NAME.patch (filtered) file.

llvm-svn: 31850

llvm-svn: 31849

llvm-svn: 31848

list

llvm-svn: 31847

llvm-svn: 31846

llvm-svn: 31845

llvm-svn: 31844

llvm-svn: 31842

llvm-svn: 31841

Also, valist should create a pointer RC reg class value, not a GPRC value.

llvm-svn: 31840

llvm-svn: 31839

llvm-svn: 31838

The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837

issues to the ground.

llvm-svn: 31836

value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(

llvm-svn: 31835

llvm-svn: 31834

llvm-svn: 31833

clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.

llvm-svn: 31832

llvm-svn: 31830

llvm-svn: 31829

llvm-svn: 31828

llvm-svn: 31827

llvm-svn: 31826

llvm-svn: 31825

2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824

llvm-svn: 31823

llvm-svn: 31822

llvm-svn: 31821

llvm-svn: 31820