Commits · eb4a55e066b6c6af99573d6ae6f9c41abfa0c110 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Dec 09, 2016
- AMDGPU: Clean up instruction bits · eb4a55e0
  Matt Arsenault authored Dec 09, 2016
  eb4a55e0
- [PPC] Add intrinsics for vector extract word and vector insert word. · 1c4109b4
  Sean Fertile authored Dec 09, 2016
  1c4109b4
- Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." · bedb5d90
  Nirav Dave authored Dec 09, 2016
  bedb5d90
- In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. · fd51ff4f
  Nirav Dave authored Dec 09, 2016
  fd51ff4f
- AMDGPU/SI: Don't mark VINTRP instructions as mayLoad · 2a48433f
  Tom Stellard authored Dec 09, 2016
  2a48433f
- [X86] Modify patterns from memory form of RCP/RSQRT/SQRT intrinsics to only... · 38b1b5d4
  Craig Topper authored Dec 09, 2016
  38b1b5d4
- [AVR] Use a more appropriate integer type for wide IN/OUT instructions · 18ae0f68
  Dylan McKay authored Dec 09, 2016
  18ae0f68
- [AVR] Add tests for a large number of pseudo instructions · a5d49dfb
  Dylan McKay authored Dec 09, 2016
  a5d49dfb
- [AVX-512] Correctly preserve the passthru semantics of the FMA scalar intrinsics · a55b483b
  Craig Topper authored Dec 09, 2016
  a55b483b
- AMDGPU: Select i16 instructions to VOP3 forms · 27c06293
  Matt Arsenault authored Dec 09, 2016
  27c06293
- [X86] Add masked versions of VPERMT2* and VPERMI2* to load folding tables. · c4f2b099
  Craig Topper authored Dec 09, 2016
  c4f2b099
- [AVX-512] Add vpermilps/pd to load folding tables. · 2aeb4564
  Craig Topper authored Dec 09, 2016
  2aeb4564
Dec 08, 2016
- [RDF] Fix incorrect lane mask calculation · 77a45576
  Krzysztof Parzyszek authored Dec 08, 2016
  77a45576
- AMDGPU: Make f16 ConstantFP legal · e96d0374
  Matt Arsenault authored Dec 08, 2016
  e96d0374
- [AMDGPU] Fix number of reserved SGPRs on CI to reflect flat scratch use · 73b54f41
  Stanislav Mekhanoshin authored Dec 08, 2016
  73b54f41
- AMDGPU: Fix commuting v_sub_u16 · 6c06a6f4
  Matt Arsenault authored Dec 08, 2016
  6c06a6f4
- [AMDGPU] Add amdgpu-unify-metadata pass · 50ea93a2
  Stanislav Mekhanoshin authored Dec 08, 2016
  50ea93a2
- IR, X86: Understand !absolute_symbol metadata on global variables. · 235c275b
  Peter Collingbourne authored Dec 08, 2016
  235c275b
- [AMDGPU] Scalarization of global uniform loads. · 18009560
  Alexander Timofeev authored Dec 08, 2016
  18009560
- LanaiInstPrinter: Prune unused libdeps. · 9ccd9666
  NAKAMURA Takumi authored Dec 08, 2016
  9ccd9666
- AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameBaseReg · 2857dc38
  Nicolai Haehnle authored Dec 08, 2016
  2857dc38
- [AVR] Add an assertion to ensure we don't emit LPM when it's unsupported · fac9ce54
  Dylan McKay authored Dec 08, 2016
  fac9ce54
- LivePhysReg: Use reference instead of pointer in init(); NFC · 0c989a89
  Matthias Braun authored Dec 08, 2016
  0c989a89
Dec 07, 2016
- GlobalISel: simplify MachineIRBuilder interface. · 05cc4859
  Tim Northover authored Dec 07, 2016
  05cc4859
- [X86] Skip over DEBUG_VALUE while looking for start of call sequence · 5842b206
  Michael Kuperstein authored Dec 07, 2016
  5842b206
- [X86] Do not assume "ri" instructions always have an immediate operand · 18092cf2
  Michael Kuperstein authored Dec 07, 2016
  18092cf2
- [X86][SSE] Remove AND -> VZEXT combine · c3c6463c
  Simon Pilgrim authored Dec 07, 2016
  c3c6463c
- [AVR] Expand 'SELECT_CC' nodes whereever possible · 99b756eb
  Dylan McKay authored Dec 07, 2016
  99b756eb
- [X86][SSE] Consistently set MOVD/MOVQ load/store/move instructions to integer domain · 8893bd95
  Simon Pilgrim authored Dec 07, 2016
  8893bd95
- [X86][XOP] Fix VPERMIL2 non-constant pool shuffle decoding (PR31296) · d5bc5c16
  Simon Pilgrim authored Dec 07, 2016
  d5bc5c16
- [AVR] Allow loading from stack slots where src and dest registers are identical · 8cec7eb6
  Dylan McKay authored Dec 07, 2016
  8cec7eb6
- AMDGPU : Add S_SETREG instructions to fix fdiv precision issues. · 8485fa09
  Tom Stellard authored Dec 07, 2016
  8485fa09
- [AArch64] Correct the check of signed 9-bit imm in isLegalAddressingMode() · f8b83404
  Haicheng Wu authored Dec 07, 2016
  f8b83404
- AMDGPU: Add llvm.amdgcn.interp.mov intrinsic · 2187bb8a
  Tom Stellard authored Dec 06, 2016
  2187bb8a
- AMDGPU: Fix crash on i16 constant expression · 269ffdac
  Matt Arsenault authored Dec 06, 2016
  269ffdac
Dec 06, 2016
- AMDGPU: Fix operand name for v_interp_* · ac066f35
  Matt Arsenault authored Dec 06, 2016
  ac066f35
- AMDGPU/SI: Set correct value for amd_kernel_code_t::kernarg_segment_alignment · 175959e3
  Tom Stellard authored Dec 06, 2016
  175959e3
- AMDGPU/SI: Don't move copies of immediates to the VALU · 00cfa747
  Tom Stellard authored Dec 06, 2016
  00cfa747
- [X86] Prefer reduced width multiplication over pmulld on Silvermont · 8bc7e4da
  Zvi Rackover authored Dec 06, 2016
  8bc7e4da
- GlobalISel: handle G_SEQUENCE fallbacks gracefully. · c1a23854
  Tim Northover authored Dec 06, 2016
  c1a23854