welcome for one.

llvm-svn: 104101

llvm-svn: 104095

Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.

The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094

opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.

llvm-svn: 104091

llvm-svn: 104090

llvm-svn: 104089

constants in registers which partially cancel out their immediate fields.

llvm-svn: 104088

of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.

llvm-svn: 104087

in the coalescer's instruction map.

llvm-svn: 104086

llvm-svn: 104085

gc attributes to be inline with Objective-C
(for radar 7925141).

llvm-svn: 104084

expressions in attributes, pragmas.

llvm-svn: 104083

function.

llvm-svn: 104082

involves extending implicit conversion sequences to model vector
conversions and vector splats, along with teaching the C++ conditional
operator-checking code about vector types.

Fixes <rdar://problem/7983501>.

llvm-svn: 104081

llvm-svn: 104080

a helper function.

llvm-svn: 104079

llvm-svn: 104078

is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.

llvm-svn: 104077

confusion with LSRInstance's RegUses member.

llvm-svn: 104076

forward declarations and definitions of structs/classes/enums.

llvm-svn: 104075

llvm-svn: 104074

llvm-svn: 104073

llvm-svn: 104068

specified.

llvm-svn: 104066

8-bit immediate field rather than one with a wider immediate field.

llvm-svn: 104064

llvm-svn: 104063

The register use operands (e.g. the first argument is passed in a 
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use.  This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.

This fixes rdar://7998435

llvm-svn: 104062

Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649

llvm-svn: 104060

Fixes build failure as well.

llvm-svn: 104059

llvm-svn: 104058

Fix up callers and users.

llvm-svn: 104057

instruction.

This can happen on ARM:

>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>

llvm-svn: 104056

design limitation in how we handle Objective-C class extensions.  This was causing the CursorVisitor
to essentially visit an @property twice (once in the @interface, the other in the class extension).
Fixes <rdar://problem/7410145>.

llvm-svn: 104055

there it may work everywhere...

llvm-svn: 104053

llvm-svn: 104052

Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.

llvm-svn: 104051

Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.

llvm-svn: 104050

llvm-svn: 104043

llvm-svn: 104041

CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".

llvm-svn: 104039