- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

llvm-svn: 27310

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27275

llvm-svn: 27272

llvm-svn: 27271

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

llvm-svn: 27257

llvm-svn: 27256

llvm-svn: 27255

For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250

integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248

- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

llvm-svn: 27245

- Other shuffle related fixes.

llvm-svn: 27244

The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240

llvm-svn: 27239

llvm-svn: 27225

llvm-svn: 27223

llvm-svn: 27222

llvm-svn: 27221

llvm-svn: 27220

llvm-svn: 27219

* Bug fixes.

llvm-svn: 27218

llvm-svn: 27212

llvm-svn: 27211

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27180

llvm-svn: 27174

llvm-svn: 27167

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27152

llvm-svn: 27150

llvm-svn: 27120

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27109