test/lit.site.cfg, not Unit/test/lit.site.cfg.

llvm-svn: 133608

llvm-svn: 133599

Patch by Wei-Ren Chen

llvm-svn: 133589

llvm-svn: 133585

to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.

llvm-svn: 133565

This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

llvm-svn: 133524

Add support for sadd.with.overflow and uadd.with.overflow intrinsics to the CBackend by emitting definitions for each intrinsic that occurs in the module.

llvm-svn: 133522

build) caused by r133435.

llvm-svn: 133509

1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

llvm-svn: 133503

ops.

This is a rewrite of the IV simplification algorithm used by
-disable-iv-rewrite. To avoid perturbing the default mode, I
temporarily split the driver and created SimplifyIVUsersNoRewrite. The
idea is to avoid doing opcode/pattern matching inside
IndVarSimplify. SCEV already does it. We want to optimize with the
full generality of SCEV, but optimize def-use chains top down on-demand rather
than rewriting the entire expression bottom-up. This was easy to do
for operations that SCEV can prove are identity function. So we're now
eliminating bitmasks and zero extends this way.

A result of this rewrite is that indvars -disable-iv-rewrite no longer
requires IVUsers.

llvm-svn: 133502

llvm-svn: 133494

llvm-svn: 133454

movd when assembling.

llvm-svn: 133452

with 32bit values.

llvm-svn: 133439

point during the development of the phi operand changes.

llvm-svn: 133436

source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )

llvm-svn: 133424

llvm-svn: 133390

llvm-svn: 133381

top level type without a specified number.  This syntax isn't documented
and blocks forward progress.

llvm-svn: 133371

llvm-svn: 133356

llvm-svn: 133349

In cases such as the attached test, where the case value for a switch
destination is used in a phi node that follows the destination, it
might be better to replace that value with the condition value of the
switch, so that more blocks can be folded away with
TryToSimplifyUncondBranchFromEmptyBlock because there are less
conflicts in the phi node.

llvm-svn: 133344

llvm-svn: 133339

type's bitwidth matches the (allocated) size of the alloca. This severely
pessimizes vector scalar replacement when the only vector type being used is
something like <3 x float> on x86 or ARM whose allocated size matches a
<4 x float>.

I hope to fix some of the flawed assumptions about allocated size throughout
scalar replacement and reenable this in most cases.

llvm-svn: 133338

for pre-2.9 bitcode files.  We keep x86 unaligned loads, movnt, crc32, and the
target indep prefetch change.

As usual, updating the testsuite is a PITA.

llvm-svn: 133337

alloca. Fixes part of <rdar://problem/9580800>.

llvm-svn: 133336

This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326

llvm-svn: 133324

range without a libcall to a new mulo<mode> libcall
that we'd have to create.

Finishes the rest of rdar://9090077 and rdar://9210061

llvm-svn: 133318

the newly created simple type is valid before checking its legality.
Re-commit the test file.

llvm-svn: 133291

Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108

llvm-svn: 133289

calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288

llvm-svn: 133275

and other backward compatibility hacks.

llvm-svn: 133273

to functions and call/invokes, not to types.

llvm-svn: 133266

llvm-svn: 133260

llvm-svn: 133256

* rounding modes for fp add, mul, sub now use .rn
* float -> int rounding correctly uses .rzi not .rni
* 32bit fdiv for sm13 uses div.rn (instead of div.approx)
* 32bit fdiv for sm10 now uses div (instead of div.approx)

Approx is not IEEE 754 compatible (and should be optionally set by a flag to the backend instead). The .rn rounding modifier is the PTX default anyway, but it's better to be explicit.

All these modifiers should be available by using __fmul_rz functions for example, but support will need to be added for this in the backend.

Patch by Dan Bailey

llvm-svn: 133253

needed since llvm-gcc 3.4 days.

llvm-svn: 133248

remove asmparser support for the old getresult instruction, which has been subsumed by extractvalue.

llvm-svn: 133247